PIC16F676-ESLASHST datasheet(45/132 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS40039F-page 45

PIC16F630/676

7.0

ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

(PIC16F676 ONLY)

The Analog-to-Digital Converter (ADC) allows conver-

sion of an analog input signal to a 10-bit binary repre-

sentation of that signal. The PIC16F676 has eight

analog inputs, multiplexed into one sample and hold

circuit. The output of the sample and hold is connected

to the input of the converter. The converter generates a

binary result via successive approximation and stores

the result in a 10-bit register. The voltage reference

used in the conversion is software selectable to either

VDD or a voltage applied by the VREF pin. Figure 7-1

shows the block diagram of the A/D on the PIC16F676.

FIGURE 7-1:

A/D BLOCK DIAGRAM

7.1

A/D Configuration and Operation

There are three registers available to control the

functionality of the A/D module:

ADCON0 (Register 7-1)

ADCON1 (Register 7-2)

ANSEL (Register 7-3)

7.1.1

ANALOG PORT PINS

The ANS7:ANS0 bits (ANSEL<7:0>) and the TRISA

bits control the operation of the A/D port pins. Set the

corresponding TRISA bits to set the pin output driver to

its high-impedance state. Likewise, set the correspond-

ing ANS bit to disable the digital input buffer.

7.1.2

CHANNEL SELECTION

There are eight analog channels on the PIC16F676,

AN0

through

AN7.

The

CHS2:CHS0

bits

(ADCON0<4:2>) control which channel is connected to

the sample and hold circuit.

7.1.3

VOLTAGE REFERENCE

There are two options for the voltage reference to the

A/D converter: either VDD is used, or an analog voltage

applied to VREF is used. The VCFG bit (ADCON0<6>)

controls the voltage reference selection. If VCFG is set,

then the voltage on the VREF pin is the reference;

otherwise, VDD is the reference.

7.1.4

CONVERSION CLOCK

The A/D conversion cycle requires 11 TAD. The source

of the conversion clock is software selectable via the

ADCS bits (ADCON1<6:4>). There are seven possible

clock options:

•FOSC/2

•FOSC/4

•FOSC/8

•FOSC/16

•FOSC/32

•FOSC/64

•FRC (dedicated internal oscillator)

For correct conversion, the A/D conversion clock

(1/TAD) must be selected to ensure a minimum TAD of

1.6

s. Table 7-1 shows a few TAD calculations for

selected frequencies.

RA0/AN0

ADC

RA1/AN1/VREF

RA2/AN2

RC0/AN4

VDD

VREF

ADON

GO/DONE

VCFG = 1

VCFG = 0

CHS2:CHS0

ADRESH ADRESL

ADFM

VSS

RC1/AN5

RC2/AN6

RC3/AN7

RA4/AN3

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

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