PIC16F676-ESLASHST datasheet(61/132 Pages) MICROCHIP

61 / 132 page

 2010 Microchip Technology Inc.

DS40039F-page 61

PIC16F630/676

9.3.5

BROWN-OUT DETECT (BOD)

The PIC16F630/676 members have on-chip Brown-out

Detect circuitry. A Configuration bit, BODEN, can

disable (if clear/programmed) or enable (if set) the

Brown-out Detect circuitry. If VDD falls below VBOD for

greater than parameter (TBOD) in Table 12-4 (see

Section 12.0

“Electrical

Specifications”),

the

Brown-out situation will reset the device. This will occur

regardless of VDD slew-rate. A Reset is not guaranteed

to occur if VDD falls below VBOD for less than parameter

(TBOD).

any

Reset

(Power-on,

Brown-out

Detect,

Watchdog, etc.), the chip will remain in Reset until VDD

rises above BVDD (see Figure 9-6). The Power-up

Timer will now be invoked, if enabled, and will keep the

chip in Reset an additional 72 ms.

If VDD drops below BVDD while the Power-up Timer is

running, the chip will go back into a Brown-out Detect

and the Power-up Timer will be re-initialized. Once VDD

rises above BVDD, the Power-up Timer will execute a

72 ms Reset.

FIGURE 9-6:

BROWN-OUT SITUATIONS

9.3.6

TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows: first,

PWRT time-out is invoked after POR has expired.

Then, OST is activated. The total time-out will vary

based on oscillator configuration and PWRTE bit

status. For example, in EC mode with PWRTE bit

erased (PWRT disabled), there will be no time-out at

all. Figure 9-7, Figure 9-8 and Figure 9-9 depict time-

out sequences.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then

bringing MCLR high will begin execution immediately

(see Figure 9-8). This is useful for testing purposes or

to synchronize more than one PIC16F630/676 device

operating in parallel.

Table 9-6 shows the Reset conditions for some special

registers, while Table 9-7 shows the Reset conditions

for all the registers.

9.3.7

POWER CONTROL (PCON) STATUS

The power CONTROL/STATUS register, PCON

(address 8Eh) has two bits.

Bit 0 is BOD (Brown-out). BOD is unknown on Power-

on Reset. It must then be set by the user and checked

on subsequent Resets to see if BOD = 0, indicating that

a brown-out has occurred. The BOD Status bit is a

“don’t care” and is not necessarily predictable if the

brown-out circuit is disabled (by setting BODEN bit = 0

in the Configuration Word).

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset must have occurred (i.e., VDD may

have gone too low).

Note:

A Brown-out Detect does not enable the

Power-up Timer if the PWRTE bit in the

Configuration Word is set.

72 ms(1)

VBOD

VDD

Internal

Reset

VBOD

VDD

Internal

Reset

72 ms(1)

<72 ms

72 ms(1)

VBOD

VDD

Internal

Reset

Note 1: 72 ms delay only if PWRTE bit is programmed to ‘0’.

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