AM79C940 datasheet(25/122 Pages) AMD

25 / 122 page

AMD

Am79C940

HOST SYSTEM INTERFACE

DBUS15–0

Data Bus (

Input/Output/3-state)

DBUS contains read and write data to and from internal

registers and the Transmit and Receive FIFOs.

ADD4–0

Address Bus

(Input)

ADD is used to access the internal registers and FIFOs

to be read or written.

R/W

Read/Write

(Input)

Indicates the direction of data flow during the MACE de-

vice

accesses.

RDTREQ

Receive Data Transfer Request

(Output)

Receive Data Transfer Request indicates that there is

data in the Receive FIFO to be read. When

RDTREQ is

asserted there will be a minimum of 16 bytes to be read

except at the completion of the frame, in which case

EOF will be asserted. RDTREQ can be programmed to

request receive data transfer when 16, 32 or 64 bytes

are available in the Receive FIFO, by programming the

Receive FIFO Watermark (RCVFW bits) in the FIFO

Configuration Control register. The first assertion of

RDTREQ will not occur until at least 64 bytes have been

received, and the frame has been verified as non runt.

Runt packets will normally be deleted from the Receive

FIFO with no external activity on

RDTREQ. When Runt

Packet Accept is enabled (RPA bit) in the User Test

RDTREQ will be asserted when the runt pack-

et completes, and the entire frame resides in the

Receive FIFO.

RDTREQ will be asserted only when En-

able Receive (ENRCV) is set in the MAC Configuration

Control register.

The RCVFW can be overridden by enabling the Low La-

tency Receive function (setting LLRCV bit) in the Re-

ceive Frame Control register, which allows

RDTREQ to

be asserted after only 12 bytes have been received.

Note that use of this function exposes the system inter-

face to premature termination of the receive frame, due

to network events such as collisions or runt packets. It is

the responsibility of the system designer to provide ade-

quate recovery mechanisms for these conditions.

TDTREQ

Transmit Data Transfer Request

(Output)

Transmit Data Transfer Request indicates there is room

in the Transmit FIFO for more data.

TDTREQ is as-

serted when there are a minimum of 16 empty bytes in

the Transmit FIFO.

TDTREQ can be programmed to re-

quest transmit data transfer when 16, 32 or 64 bytes are

available in the Transmit FIFO, by programming the

Transmit FIFO Watermark (XMTFW bits) in the FIFO

Configuration

Control

TDTREQ will be

asserted only when Enable Transmit (ENXMT) is set in

the MAC Configuration Control register.

FDS

FIFO Data Select

(Input)

FIFO Data Select allows direct access to the transmit or

Receive FIFO without use of the ADD address bus.

FDS

must be activated in conjunction with R/

W. When the

MACE device samples R/

W as high and FDS low, a read

cycle from the Receive FIFO will be initiated. When the

MACE chip samples R/

W and FDS low, a write cycle to

the Transmit FIFO will be initiated. The

CS line should

be inactive (high) when FIFO access is requested using

the

FDS pin. If the MACE device samples both CS and

FDS as active simultaneously, no cycle will be exe-

cuted, and

DTV will remain inactive.

DTV

Data Transfer Valid

(Output/3-state)

When asserted, indicates that the read or write opera-

tion has completed successfully. The absence of

DTV at

the termination of a host access cycle on the MACE de-

vice indicates that the data transfer was unsuccessful.

DTV need not be used if the system interface can guar-

antee that the latency to

TDTREQ and RDTREQ asser-

tion and de-assertion will not cause the Transmit FIFO

to be over-written or the Receive FIFO to be over-read.

In this case, the latching or strobing of read or write data

can be synchronized to the SCLK input rather than to the

DTV output.

EOF

End Of Frame

(Input/Output/3–state)

End Of Frame will be asserted by the MACE device

when the last byte/word of frame data is read from the

Receive FIFO, indicating the completion of the frame

data field for the receive message. End Of Frame must

be asserted low to the MACE device when the last byte/

word of the frame is written into the Transmit FIFO.

BE1–0

Byte Enable

(Input)

Used to indicate the active portion of the data transfer to

or from the internal FIFOs. For word (16-bit) transfers,

both

BE0 and BE1 should be activated by the external

host/controller. Single byte transfers are performed by

identifying the active data bus byte and activating only

one of the two signals. The function of the

BE1–0 pins is

programmed using the BSWP bit (BIU Configuration

Control register, bit 6).

BE1–0 are not required for ac-

cesses to MACE device registers.

Chip Select

(Input)

Used to access the MACE device FIFOs and internal

registers locations using the ADD address bus. The

FIFOs may alternatively be directly accessed without

supplying the FIFO address, by using the

FDS and

W pins.

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