AM79C940 datasheet(43/122 Pages) AMD

43 / 122 page

AMD

Am79C940

receiver is capable of changing the initial or previous po-

larity configuration based on the most recent ETD polar-

ity.

On receipt of the first packet with valid ETD following re-

set or Link Fail, the MACE device will utilize the inferred

polarity information to configure its RXD

± input, regard-

less of its previous state. On receipt of a second packet

with a valid ETD with correct polarity, the detection/cor-

rection algorithm will

lock-in the received polarity. If the

second (or subsequent) packet is not detected as con-

firming the previous polarity decision, the most recently

detected ETD polarity will be used as the default. Note

that packets with invalid ETD have no effect on updating

the previous polarity decision. Once two consecutive

packets with valid ETD have been received, the MACE

device will disable the detection/correction algorithm

until either a Link Fail condition occurs or a hardware or

software reset occurs.

During polarity reversal, the

RXPOL pin should be exter-

nally pulled HIGH and the Reversed Polarity bit

(REVPOL in the PHY Configuration Control register) will

be set. During normal polarity conditions, the

RXPOL

pin is driven LOW (capable of directly driving a Polarity

OK LED using an integrated 12 mA driver) and the REV-

POL bit will be cleared.

If desired, the polarity correction function can be dis-

abled by setting the Disable Auto Polarity Correction bit

(DAPC bit in the PHY Configuration Control register).

However, the polarity detection portion of the algorithm

continues to operate independently, and the

RXPOL pin

and the REVPOL bits will reflect the polarity state of the

receiver.

Twisted Pair Interface Status

Three outputs (TXEN, RXCRS and CLSN) indicate

whether the MACE device is transmitting (MENDEC

to Twisted Pair), receiving (Twisted Pair to MENDEC),

or in a collision state with both functions active

simultaneously.

The MACE device will power up in the Link Fail state.

The normal algorithm will apply to allow it to enter the

Link Pass state. On power up, the TXEN, RXCRS and

CLSN) pins will be in a high impedance state until they

are enabled by setting the Enable PLS I/O bit (ENPLSIO

in the PLS Configuration Control register) and the

10BASE-T port enters the Link Pass state.

In the Link Pass state, transmit or receive activity which

passes the pulse width/amplitude requirements of the

± or RXD± inputs, will be indicated by the TXEN or

RXCRS pin respectively going active. TXEN, RXCRS

and CLSN are all asserted during a collision.

In the Link Fail state, TXEN, RXCRS and CLSN are

inactive.

In jabber detect mode, the MACE device will activate the

CLSN pin, disable TXEN (regardless of Manchester

data output from the MENDEC), and allow the RXCRS

pin to indicate the current state of the RXD

± pair. If there

is no receive activity on RXD

±, only CLSN will be active

during jabber detect. If there is RXD

± activity, both

CLSN and RXCRS will be active.

If the

SLEEP pin is asserted (regardless of the program-

ming of the AWAKE or RWAKE bits in the PHY Configu-

ration Control register), the TXEN, RXCRS and CLSN

outputs will be placed in a high impedance state.

Collision Detect Function

Simultaneous activity (presence of valid data signals)

from both the internal MENDEC transmit function (indi-

cated externally by TXEN active) and the twisted pair

RXD

± pins constitutes a collision, thereby causing an

external indication on the CLSN pin, and an internal indi-

cation which is returned to the MAC core. The TXEN,

RXCRS and CLSN pins are driven high during collision.

Signal Quality Error (SQE) Test

(Heartbeat) Function

The SQE Test message (a 10 MHz burst normally re-

turned on the AUI CI

± pair at the end of every transmis-

sion) is intended to be a self-test indication to the DTE

that the MAU collision circuitry is functional and the AUI

cable/connection is intact. This has minimal relevance

when the 10BASE-T MAU is embedded in the LAN con-

troller. A Collision Error (CERR bit in the Interrupt Regis-

ter) will be reported only when the 10BASE-T port is in

the link fail state, since the collision circuit of the MAU

will be disabled, causing the absence of the SQE Test

message. In GPSI mode the external encoder/decoder

is responsible for asserting the CLSN pin after each

transmission. In DAI mode SEQ Test has no relevance.

Jabber Function

The Jabber function inhibits the twisted pair transmit

function of the MACE device if the TXD

±/TXP± circuits

are active for an excessive period (20–150 ms). This

prevents any one node from disrupting the network due

to a stuck-on or faulty transmitter. If this maximum trans-

mit time is exceeded, the data path through the

10BASE-T transmitter circuitry is disabled (although

Link Test pulses will continue to be sent), the CLSN pin

is asserted, the Jabber bit (JAB in the Interrupt Register)

is set and the

INTR pin will be asserted providing the

JABM bit (Interrupt Mask Register) is cl eared. Once the

internal transmit data stream from the MENDEC stops

(TXEN deasserts), an

unjab time of 250–750 ms will

elapse before the MACE device deasserts the CLSN in-

dication and re-enables the transmit circuitry.

When jabber is detected, the MACE device will assert

the CLSN pin, de-assert the TXEN pin (regardless of

AM79C940 Datasheet(PDF) 43 Page - Advanced Micro Devices

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