AM79C940 datasheet(53/122 Pages) AMD

53 / 122 page

AMD

Am79C940

Receive Function Programming

The Receive Frame Control register allows program-

ming of the automatic pad field stripping feature and the

configuration of the Match/Reject (M/

R) pin. ASTRP

RCV and M/

R must be static when the receive function

is enabled (ENRCV = 1). The receiver should be dis-

abled before (re-) programming these options.

The EADI port can be used to permit reception of frames

to commence whilst external address decoding takes

place. The M/

R bit defines the function of the EAM/R pin,

and hence whether frames will be accepted or rejected

by the external address comparison logic.

The programming of additional receive attributes are

distributed between the FIFO and MAC Configuration

Control registers, and the User Test Register.

All receive frames can be accepted by setting the PROM

bit (bit 7) in the MAC Configuration Control register.

When PROM is set, the MACE device will attempt to re-

ceive all messages, subject to minimum frame enforce-

ment. Setting PROM will override the use of the EADI

port to force the rejection of unwanted messages. See

the sections

External Address Detection Interface for

more details.

The point at which

RDTREQ is asserted in relation to the

number of bytes of a frame that are present in the Re-

ceive FIFO (RCVFIFO) is controlled by the RCVFW bits

in the FIFO Configuration Control register, or the

LLRCV bit in the Receive Frame Control register.

RDTREQ will be asserted when one of the following

conditions is true:

(i) There are at least 64 bytes in the RCVFIFO.

(ii) The received packet has passed the 64 byte mini-

mum criteria, and the number of bytes in the

RCVFIFO is greater than or equal to the threshold

set by the RCVFW (16 or 32 bytes).

(iii) A receive packet has completed, and part or all of it

is present in the RCVFIFO.

(iv) The LLRCV bit has been set and greater than

12-bytes of at least 8 bytes have been received.

Note that if the RCVFW is set below the 64-byte limit, the

MACE device will still require 64-bytes of data to be re-

ceived before the initial assertion of

RDTREQ. Subse-

quently,

RDTREQ will be asserted at any time the

RCVFW threshold is exceeded. The only times that the

RDTREQ will be asserted when there are not at least an

initial 64-bytes of data in the RCVFIFO are:

(i) When the ASTRP RCV bit has been set in the Re-

ceive Frame Control register, and the pad is auto-

matically stripped from a minimum length packet.

(ii) When the RPA bit has been set in the User Test

been received.

(iii) When the LLRCV bit has been set in the Receive

Frame Control register, and at least 12-bytes (after

SFD) has been received.

No preamble/SFD bytes are loaded into the Receive

FIFO. All references to bytes past through the receive

FIFO are received after the preamble/SFD sequence.

Depending on the bus latency of the system, RCVFW

can be set to ensure that the RCVFIFO does not over-

flow before more data is read. When the entire frame is

in the RCVFIFO,

RDTREQ will be asserted regardless

of the value in RCVFW. The default value of RCVFW is

64-bytes after hardware or software reset.

The receive operation of the MACE device can be halted

at any time by clearing the ENRCV bit in the MAC Con-

figuration Control register. Note that any receive frame

currently in progress will be accepted normally, and the

MACE device will disable the receive process once the

message has completed. The Missed Packet Count

(MPC) will be incremented for subsequent packets that

would have normally been passed to the host, and are

now ignored due to the disabled state of the receiver.

Note that clearing the ENRCV bit disables the assertion

RDTREQ. If ENRCV is cleared during receive activity

and remains cleared for a long time and if the tail end of

the receive frame currently in progress is longer than the

amount of space available in the Receive FIFO, Receive

FIFO overflow will occur. However, even with

RDTREQ

deasserted, if there is valid data in the Receive FIFO to

be read, successful slave reads to the Receive FIFO

can be executed (indicated by valid

DTV). It is the host’s

responsibility to avoid the overflow situation.

Automatic Pad Stripping

During reception of a frame the pad field can be stripped

automatically. ASTRP RCV = 1 enables the automatic

pad stripping feature. The pad field will be stripped be-

fore the frame is passed to the FIFO, thus preserving

FIFO space for additional frames. The FCS field will also

be stripped, since it is computed at the transmitting sta-

tion based on the data and pad field characters, and will

be invalid for a receive frame that has the pad charac-

ters stripped.

The number of bytes to be stripped is calculated from

the embedded length field (as defined in the IEEE 802.3

definition) contained in the packet. The length indicates

the actual number of LLC data bytes contained in the

message. Any received frame which contains a length

field less than 46 bytes will have the pad field stripped.

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