AM79C940 datasheet(52/122 Pages) AMD

52 / 122 page

AMD

Am79C940

(nominal 10 MHz sequence) to be returned via the CI

pair, within a 40 network bit time period after DI

± goes

inactive. If the CI

± input is not asserted within the 40 net-

work bit time period following the completion of trans-

mission, then the MACE device will set the CERR bit (bit

5) in the Interrupt Register. The

INTR pin will be acti-

vated if the corresponding mask bit CERRM = 0.

When the GPSI port is selected, the MACE device will

expect the CLSN input pin to be asserted 40 bit times af-

ter the transmission has completed (after TXEN output

pin has gone inactive). When the DAI port has been se-

lected, the CERR bit will not be reported. A transceiver

connected via the DAI port is not expected to support

the SQE Test Message feature.

Host related transmit exception conditions include:

(a) Overflow caused by excessive writes to the Trans-

mit FIFO (

DTV will not be issued if the Transmit

FIFO is full).

(b) Underflow caused by lack of host writes to the

Transmit FIFO.

(a) The host may continue to write to the Transmit FIFO

after the

TDTREQ has been de-asserted, and can safely

do so on the basis of knowledge of the number of free

bytes remaining (set by XMTFW in the FIFO

Configuration Control register). If however the host sys-

tem continues to write data to the point that no additional

FIFO space exists, the MACE device will not return the

DTV signal and hence will effectively not acknowledge

acceptance of the data. It is the host’s responsibility to

ensure that the data is re-presented at a future time

when space exists in the Transmit FIFO, and to track the

actual data written into the FIFO.

(b) If the host fails to respond to the

TDTREQ from the

MACE device before the Transmit FIFO is emptied, a

FIFO underrun will occur. The MACE device will in this

case terminate the network transmission in an orderly

sequence. If less than 512 bits have been transmitted

onto the network the transmission will be terminated im-

mediately, generating a runt packet. If greater than 512

bits have been transmitted, the message will have the

current CRC inverted and appended at the next byte

boundary, to guarantee an FCS error is detected at the

receiving station. The MACE device will report this con-

dition to the host by de-asserting the

TDTREQ pin, set-

ting the UFLO and XMTSV bits (in the Transmit Frame

Status) and the XMTINT bit (in the Interrupt Register),

and asserting the

INTR pin providing the corresponding

XMTINTM bit (in the Interrupt Mask Register) is cleared.

Once the XMTINT condition has been externally recog-

nized, the Transmit Frame Counter (XMTFC) can be

read to determine whether the tail end of the frame that

suffers the UFLO error is still in the host memory (i.e.,

when XMTFC = 0). In the case of FIFO underrun, this

will definitely be the case and the host is responsible for

ensuring that the tail end of the frame does not get writ-

ten into the FIFO and does not get transmitted as a

whole frame. It is recommended that the host clear the

tail end of the frame from the host memory before re-

questing the XMTFS read so that after the XMTFS read,

when the MACE device re-asserts

TDTREQ, the tail end

of the frame does not get written into the FIFO. The

Transmit Frame Status read will indicate that the UFLO

error occurred. The read operation on the Transmit

Frame Status will update the FIFO read and write point-

ers and the entire transmit path will be reset (which will

update the Transmit FIFO watermark with the current

XMTFW value in the FIFO Configuration Control regis-

ter).

TDTREQ will not be re-asserted until the Transmit

Frame Status has been read.

Frame Status for up to two packets. If the host fails to

read the Transmit Frame Status and both internal

entries become occupied, the MACE device will not

commence any subsequent transmit frames to prevent

overwriting of the internally stored values. This will

occur regardless of the number of bytes written to the

Transmit FIFO.

RECEIVE OPERATION

The receive operation and features of the MACE device

are controlled by programmable options. These options

are programmed through the BIU, FIFO and MAC Con-

figuration Control registers.

Parameters controlled by the MAC Configuration Con-

trol register are generally programmed only once, dur-

ing initialization, and are therefore static during the

normal operation of the MACE device (see the Media

Access Control section for a detailed description). The

features controlled by the FIFO Configuration Control

programmed without performing a reset on the part. The

host is responsible for ensuring that no data is present in

the Receive FIFO when re-programming the receive

attributes.

Receive FIFO Read

The Receive FIFO is accessed by performing a host

generated read sequence on the MACE device. See the

Slave Access Operation-Read Access section and the

AC Waveforms section, Host System Interface, figures:

”2 Cycle Receive FIFO/Register Read Timing” and ”3

Cycle Receive FIFO/Register Read Timing” for details

of the read access timing.

Note that

EOF will be asserted by the MACE device dur-

ing the last data byte/word transfer.

AM79C940 Datasheet(PDF) 52 Page - Advanced Micro Devices

AM79C940 Datasheet(HTML) 52 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL