AM79C940 datasheet(37/122 Pages) AMD

37 / 122 page

AMD

Am79C940

will be set and the transmit message will be flushed from

the XMTFIFO. The RTRY condition will cause the de-

assertion of

TDTREQ, and the assertion of the INTR pin,

providing the XMTINTM bit is cleared.

If a collision is detected after 512 bit times have been

transmitted, the collision is termed a late collision. The

MACE device will abort the transmission, append the

jam sequence and set the LCOL bit in the Transmit

Frame Status. No retry attempt will be scheduled on de-

tection of a late collision, and the XMTFIFO will be

flushed. The late collision condition will cause the de-as-

sertion of

TDTREQ, and the assertion of the INTR pin,

providing the XMTINTM bit is cleared.

The IEEE 802.3 Standard requires use of a

truncated bi-

nary exponential backoff algorithm which provides a

controlled pseudo random mechanism to enforce the

collision backoff interval, before re-transmission is

attempted.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

“At the end of enforcing a collision (jamming),

the CSMA/CD sublayer delays before attempt-

ing to re-transmit the frame. The delay is an in-

teger multiple of slotTime. The number of slot

times to delay before the nth re-transmission at-

tempt is chosen as a uniformly distributed ran-

dom integer r in the range:

≤ r ≤ 2k, where k = min (n,10).”

The MACE device implements a random number gen-

erator, configured to ensure that nodes experiencing a

collision, will not have their retry intervals track identi-

cally, causing retry errors.

The MACE device provides an alternative algorithm,

which suspends the counting of the slot time/IPG during

the time that receive carrier sense is detected. This aids

in networks where large numbers of nodes are present,

and numerous nodes can be in collision. It effectively ac-

celerates the increase in the backoff time in busy

networks, and allows nodes not involved in the collision

to access the channel whilst the colliding nodes await a

reduction in channel activity. Once channel activity is

reduced, the nodes resolving the collision time-out their

slot time counters as normal.

If a receive message suffers a collision, it will be either a

runt, in which case it will be deleted in the Receive FIFO,

or it will be marked as a receive late collision, using the

CLSN bit in the Receive Frame Status register. All

frames which suffer a collision within the slot time will be

deleted in the Receive FIFO without requesting host in-

tervention, providing that the LLRCV bit (Receive Frame

Control) is not set. Runt packets which suffer a collision

will be aborted regardless of the state of the RPA bit

(User Test Register). If the collision commences after

the slot time, the MACE device receiver will stop send-

ing collided packet data to the Receive FIFO and the

packet data read by the system will contain the amount

of data received to the point of collision; the CLSN bit in

the Receive Frame Status register will indicate the re-

ceive late collision. Note that the Receive Message Byte

Count will report the total number of bytes during the re-

ceive activity, including the collision.

In all normal receive collision cases, the MACE device

eliminates the transfer of packet data across the host

bus. In a receive late collision condition, the MACE chip

minimizes the amount transferred. These functions pre-

serve bus bandwidth utilization.

Manchester Encoder/Decoder (MENDEC)

The integrated Manchester Encoder/Decoder provides

the PLS (Physical Signaling) functions required for a

fully compliant IEEE 802.3 station. The MENDEC block

contains the AUI, DAI

interfaces, and supports the

10BASE-T interface; all of which transfer data to appro-

priate transceiver devices in Manchester encoded for-

mat. The MENDEC provides the encoding function for

data to be transmitted on the network using the high ac-

curacy on-board oscillator, driven by either the crystal

oscillator or an external CMOS level compatible clock

generator. The MENDEC also provides the decoding

function from data received from the network. The MEN-

DEC contains a Power On Reset (POR) circuit, which

ensures that all analog portions of the MACE device are

forced into their correct state during power up, and pre-

vents erroneous data transmission and/or reception

during this time.

External Crystal Characteristics

When using a crystal to drive the oscillator, the following

crystal specification should be used to ensure less than

±0.5 ns jitter at DO±:

AM79C940 Datasheet(PDF) 37 Page - Advanced Micro Devices

AM79C940 Datasheet(HTML) 37 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL