AM79C940 datasheet(68/122 Pages) AMD

68 / 122 page

AMD

Am79C940

not implement Link Test, this

function can be disabled by set-

ting the DLNKTST bit. With Link

Test disabled (DLNKTST = 1),

the data driver, receiver and

loopback functions as well as col-

lision detection remain enabled

irrespective of the presence or

absence of data or link pulses on

the RXD

± pair. The transmitter

will continue to generate link beat

pulses during periods of transmit

data inactivity. Set by hardware

or software reset.

Bit 6

DLNKTST

Disable Link Test. When set, the

integrated

10BASE-T

trans-

ceiver will be forced into the link

pass state, regardless of receive

link test pulses or receive packet

activity.

Bit 5

REVPOL

Reversed Polarity. Indicates the

receive polarity of the RD

± pair.

When normal polarity is de-

tected, the REVPOL bit will be

cleared, and the

RXPOL pin (ca-

pable of driving a

Polarity OK

LED) will be driven LOW. When

reverse polarity is detected, the

REVPOL bit will be set, and the

RXPOL pin should be externally

pulled HIGH.

Bit 4

DAPC

Disable Auto Polarity Correction.

When set, the automatic polarity

correction will be disabled. Polar-

ity detection and indication will

still be possible via the

RXPOL

pin.

Bit 3

LRT

Low Receive Threshold. When

set, the threshold of the twisted

pair receiver will be reduced by

4.5 dB, to allow extended dis-

tance operation.

Bit 2

ASEL

Auto Select. When set, the

PORTSEL [1–0] bits are overrid-

den, and the MACE device will

automatically select the operat-

ing media interface port. When

the 10BASE-T transceiver is in

the link pass state (due to receiv-

ing valid packet data and/or Link

Test pulses or the DLNKTST bit

is set), the 10BASE-T port will be

used. When the 10BASE-T port

is in the link fail state, the AUI port

will be used. Switching between

the ports will not occur during

transmission in order to avoid

any type of fragment generation.

Bit 1

RWAKE

Remote Wake. When set prior to

the

SLEEP pin being activated,

the AUI and 10BASE-T receiver

sections and the EADI port will

continue to operate even during

SLEEP. Incoming packet activity

will be passed to the EADI port

pins permitting detection of spe-

cific frame contents used to

initiate a wake-up sequence.

RWAKE must be programmed

prior to

SLEEP being asserted

for this function to operate.

RWAKE

not

cleared

SLEEP, only by activation of the

SWRST bit or

RESET pin.

Bit 0

AWAKE

Auto Wake. When set prior to the

SLEEP pin being activated, the

10BASE-T receiver section will

continue to operate even during

SLEEP, and will activate the

LNKST pin if Link Pass is de-

tected. AWAKE must be pro-

grammed prior to

SLEEP being

asserted for this function to oper-

ate. AWAKE is not cleared by

SLEEP, only by activation of the

SWRST bit or

RESET pin.

Chip Identification Register

(CHIPID [15–00])

(REG ADDR 16 &17)

This 16-bit value corresponds to the specific version of

the MACE device being used. The value will be pro-

grammed to X940h, where

X is a value dependent on

version.

CHIPID [07–00]

CHIPID [15–08]

Internal Address

Configuration (IAC)

(REG ADDR 18)

This register allows access to and from the multi-byte

Physical Address and Logical Address Filter locations,

using only a single byte location.

The MACE device will reset the IAC register PHYADDR

and LOGADDR bits after the appropriate number of

read or write cycles have been executed on the Physical

Address Register or the Logical Address Filter. Once

the LOGADDR bit is set, the MACE device will reset the

bit after 8 read or write operations have been performed.

Once the PHYADDR bit is set, the MACE device will re-

set the bit after 6 read or write operations have been per-

formed. The MACE device makes no distinction

between read or write operations, advancing the inter-

nal address RAM pointer with each access. If both

PHYADDR and LOGADDR bits are set, the MACE de-

vice will accept only the LOGADDR bit. If the PHYADDR

bit is set and the Logical Address Filter location is ac-

cessed, a

DTV will not be returned. Similarly, if the

LOGADDR bit is set and the Physical Address Register

location is accessed,

DTV will not be returned.

PHYADDR or LOGADDR can be set in the same cycle

as ADDRCHG.

AM79C940 Datasheet(PDF) 68 Page - Advanced Micro Devices

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