AM79C940 datasheet(63/122 Pages) AMD

63 / 122 page

AMD

Am79C940

the transmission of a packet and

updated the Transmit Frame

Status. The

INTR pin will be acti-

vated if the corresponding mask

bit XMTINTM = 0.

XMTINT is READ/CLEAR only. It

is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by activa-

tion of the

RESET pin or SWRST

bit.

Interrupt Mask Register (IMR)

(REG ADDR 9)

This register contains the mask bits for the interrupts.

Read/write operations are permitted. Writing a one into

a bit will mask the corresponding interrupt. Writing a

zero to any previously set bit will unmask the corre-

sponding interrupt. Bit assignments for the register are

as follows:

RES

CERRM RCVCCOM RNTPCOM

MPCOM

RCVINTM

BABLM

XMTINTM

Bit

Name

Description

Bit 7

JABM

Jabber Error Mask. JABM is the

mask for JAB. The

INTR pin will

not be asserted by the MACE de-

vice regardless of the state of the

JAB bit, if JABM is set. It is

cleared by activation of the

RE-

SET pin or SWRST bit.

Bit 6

BABLM

Babble Error Mask. BABLM is

the mask for BABL. The

INTR pin

will not be asserted by the MACE

device regardless of the state of

the BABL bit, if BABLM is set. It is

cleared by activation of the

RESET pin or SWRST bit.

Bit 5

CERRM

Collision Error Mask. CERRM is

the mask for CERR. The

INTR

pin will not be asserted by the

MACE device regardless of the

state of the CERR bit, if CERRM

is set. It is cleared by activation of

the

RESET pin or SWRST bit.

Bit 4

RCVCCOM Receive Collision Count Over-

flow Mask. RCVCCOM is the

mask for RCVCCO(Receive Col-

lision Count Overflow). The

INTR

pin will not be asserted by the

MACE device regardless of the

state of the RCVCCO bit, if

RCVCCOM is set. It is cleared by

activation of the

RESET pin or

SWRST bit.

Bit 3

RNTPCOM Runt Packet Count Overflow

Mask. RNTPCOM is the mask for

RNTPCO (Runt Packet Count

Overflow). The

INTR pin will not

be asserted by the MACE device

regardless of the state of the

RNTPCO bit, if RNTPCOM is set.

It is cleared by activation of the

RESET pin or SWRST bit.

Bit 2

MPCOM

Missed Packet Count Overflow

Mask. MPCOM is the mask for

MPCO (Missed Packet Count

Overflow). The

INTR pin will not

be asserted by the MACE device

regardless of the state of the

MPCO bit, if MPCOM is set. It is

cleared by activation of the

RESET pin or SWRST bit.

Bit 1

RCVINTM

Receive

Interrupt

Mask.

RCVINTM

the

mask

for

RCVINT. The

INTR pin will not be

asserted by the MACE device re-

gardless of the state of the

RCVINT bit, if RCVINTM is set. It

is cleared by activation of the

RESET pin or SWRST bit.

Bit 0

XMTINTM

Transmit

Interrupt

Mask.

XMTINTM

the

mask

for

XMTINT. The

INTR pin will not be

asserted by the MACE device re-

gardless of the state of the

XMTINT bit, if XMTINT is set. It is

cleared by activation of the

RE-

SET pin or SWRST bit.

Poll Register (PR)

(REG ADDR 10)

This register contains copies of internal status bits to

simplify a host implementation which is non-interrupt

driven. The register is read only, and its status is unaf-

fected by read operations. All register bits are cleared by

hardware or software reset. Bit assignments are as fol-

lows:

XMTSV

TDTREQ

RDTREQ

RES

Bit

Name

Description

Bit 7

XMTSV

Transmit Status Valid. Transmit

Status Valid indicates that the

Transmit Frame Status is valid.

Bit 6

TDTREQ

Transmit Data Transfer Request.

An internal indication of the cur-

rent request status of the Trans-

mit FIFO. TDTREQ is set when

the external

TDTREQ signal is

asserted.

AM79C940 Datasheet(PDF) 63 Page - Advanced Micro Devices

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