AM79C940 datasheet(62/122 Pages) AMD

62 / 122 page

AMD

Am79C940

vated if the corresponding mask

bit BABLM = 0.

BABL is READ/CLEAR only, and

is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by activa-

tion of the

RESET pin or SWRST

bit.

Bit 5

CERR

Collision Error. CERR indicates

the absence of the Signal Quality

Error Test (SQE Test) message

after a packet transmission. The

SQE Test message is a trans-

ceiver test feature. Detection de-

pends on the MACE network

interface selected. In all cases,

CERR will be set if the MACE de-

vice failed to observe the SQE

Test message within 20 network

bit times after the packet trans-

mission ended. When CERR is

set, the

INTR pin will be activated

if the corresponding mask bit

CERRM = 0.

When the AUI port is selected,

the SQE Test message is re-

turned over the CI

± pair as a brief

(5–15 bit times) burst of 10 MHz

activity. When the 10BASE-T

port is selected, CERR will be re-

ported after a transmission only

when the internal transceiver is in

the link fail state (

LNKST pin =

HIGH). When the GPSI port is

selected, the CLSN pin must be

asserted by the external en-

coder/decoder to provide the

SQE Test function. When the

DAI port is selected, CERR will

not be reported at any time.

CERR is READ/CLEAR only. It is

set by the MACE and reset when

read. Writing has no effect. It is

also cleared by activation of the

RESET pin or SWRST bit.

Bit 4

RCVCCO

Receive Collision Count Over-

flow. Indicates that the Receive

Collision Count register rolled

over at a value of 255 receive col-

lisions. Receive collisions are de-

fined as received frames which

suffered a collision. The

INTR pin

will be activated if the corre-

sponding mask bit RCVCCOM =

0. Note that the RCVCC value re-

turned in the Receive Frame

Status (RFS3) will freeze at a

value of 255, whereas this regis-

ter based version of RCVCC

(REG ADDR 27) is free running.

RCVCCO is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by assert-

ing the

RESET pin or SWRST bit.

Bit 3

RNTPCO

Runt Packet Count Overflow. In-

dicates that the Runt Packet

Count register rolled over at a

value of 255 runt packets. Runt

packets are defined as received

frames which passed the internal

address match criteria but did not

contain a minimum of 64-bytes of

data after SFD. The

INTR pin will

be activated if the correspond-

ing mask bit RNTPCOM = 0.

Note that the RNTPC value re-

turned in the Receive Frame

Status (RFS2) will freeze at a

value of 255, whereas this regis-

ter based version of RNTPC

(REG ADDR 26) is free running.

RNTPCO is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by assert-

ing the

RESET pin or SWRST bit.

Bit 2

MPCO

Missed Packet Count Overflow.

Indicates that the Missed Packet

Count register rolled over at a

value of 255 missed frames.

Missed frames are defined as re-

ceived frames which passed the

internal address match criteria

but were missed due to a Re-

ceive FIFO overflow, the receiver

being disabled (ENRCV = 0) or

excessive

receive

frame

count (RCVFC > 15). The

INTR

pin will be activated if the corre-

sponding mask bit MPCOM = 0.

MPCO is READ/CLEAR only. It

is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by assert-

ing the

RESET pin or SWRST bit.

Bit 1

RCVINT

Receive Interrupt. Indicates that

the host read the last byte/word

of a packet from the Receive

FIFO. The Receive Frame Status

is available immediately on the

next host read operation. The

INTR pin will be activated if the

corresponding

mask

bit

RCVINTM = 0.

RCVINT is READ/CLEAR only. It

is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by activa-

tion of the

RESET pin or SWRST

bit.

Bit 0

XMTINT

Transmit Interrupt. Indicates that

the MACE device has completed

AM79C940 Datasheet(PDF) 62 Page - Advanced Micro Devices

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