AM79C940 datasheet(57/122 Pages) AMD

57 / 122 page

AMD

Am79C940

USER ACCESSIBLE REGISTERS

The following registers are provided for operation of the

MACE device. All registers are 8-bits wide unless other-

wise stated. Note that all reserved register bits should

be written as zero.

Receive FIFO (RCVFIFO)

(REG ADDR 0)

RCVFIFO [15–0]

This register provides a 16-bit data path from the Re-

ceive FIFO. Reading this register will read one word/

byte from the Receive FIFO. The RCVFIFO should only

be read when Receive Data Transfer Request

(

RDTREQ) is asserted. If the RCVFIFO location is read

before 64-bytes are available in the RCVFIFO (or

12-bytes in the case that LLRCV is set in the Receive

Frame Control register),

DTV will not be returned. Once

the 64-byte threshold has been achieved and

RDTREQ

is asserted, the de-assertion of

RDTREQ does not pre-

vent additional data from being read from the RCVFIFO,

but indicates the number of additional bytes which are

present,

before

the

RCVFIFO

emptied,

and

subsequent reads will not return

DTV (see the FIFO

Sub-System section for additional details). Write opera-

tions to this register will be ignored and

DTV will not be

returned.

Byte transfers from the RCVFIFO are supported, and

will be fully aligned to the target memory architecture,

defined by the BSWP bit in the BIU Configuration Con-

trol register. The Byte Enable inputs (

BE1–0) will define

which half of the data bus should be used for the trans-

fer. The external host/controller will be informed that the

last byte/word of data in a receive frame is being read

from the RCVFIFO, when the MACE device asserts the

EOF signal.

Transmit FIFO (XMTFIFO)

(REG ADDR 1)

XMTFIFO [15–0]

This register provides a 16-bit data path to the Transmit

FIFO. Byte/word data written to this register will be

placed in the Transmit FIFO. The XMTFIFO can be writ-

ten at any time the Transmit Data Transfer Request

(

TDTREQ) is asserted. The de-assertion of TDTREQ

does not prevent data being written to the XMTFIFO, but

indicates the number of additional write cycles which

can take place, before the XMTFIFO is filled, and

subsequent writes will not return

DTV (see the FIFO

Sub-System section for additional details). Read opera-

tions to this register will be ignored and

DTV will not be

returned.

Byte transfers to the XMTFIFO are supported, and ac-

cept data from the source memory architecture to en-

sure the correct byte ordering for transmission, defined

by the BSWP bit in the MAC Configuration Control regis-

ter. The Byte Enable inputs (

BE1–0) will define which

half of the data bus should be used for the transfer. The

use of byte transfers have implications on the latency

time provided by the XMTFIFO (see the

FIFO Sub-

System section for additional details). The external host/

controller must indicate the last byte/word of data in a

transmit frame is being written to the XMTFIFO, by as-

serting the

EOF signal.

Transmit Frame Control (XMTFC)

(REG ADDR 2)

The Transmit Frame Control register is latched inter-

nally on the last write to the Transmit FIFO for each indi-

vidual packet, when

EOF is asserted. This permits

automatic transmit padding and FCS generation on a

packet-by-packet basis.

DRTRY

RES

DXMTFCS

RES

APAD XMT

RES

Bit

Name

Description

Bit 7

DRTRY

Disable Retry. When DRTRY is

set, the MACE device will provide

a single transmission attempt for

the packet, all further retries will

be suspended. In the case of a

collision during the attempt, a

Retry Error (RTRY) will be re-

ported in the Transmit Status.

With DRTRY cleared, the MACE

device will attempt up to 15 re-

tries (16 attempts total) before in-

dicating a Retry Error. DRTRY is

cleared by activation of the

RE-

SET pin or SWRST bit. DRTRY is

sampled

during

the

transmit

process when a collision occurs.

DRTRY should not be changed

whilst data remains in the Trans-

mit FIFO since this may cause an

unpredictable retry response to a

collision.

Once

the

Transmit

FIFO is empty, DRTRY can be

reprogrammed.

Bit 6–4 RES

Reserved. Read as zeroes. Al-

ways write as zeroes.

Bit 3

DXMTFCS

Disable Transmit FCS. When

DXMTFCS = 0 the transmitter

will generate and append an FCS

to the transmitted frame. When

DXMTFCS = 1, no FCS will be

appended to the transmitted

frame, providing that APAD XMT

is also clear. If APAD XMT is set,

the calculated FCS will be ap-

pended to the transmitted mes-

sage regardless of the state of

DXMTFCS.

The

value

DXMTFCS for each frame is pro-

grammed when

EOF is asserted

to transfer the last byte/word for

the transmit packet to the FIFO.

DXMTFCS

cleared

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