PM6652 datasheet(33/53 Pages) STMICROELECTRONICS

33 / 53 page

PM6652

Device description

Doc ID 16867 Rev 5

33/53

capacitor, i.e. RA//RB1, and the resulting voltage drop is found on the VCORE output voltage,

in agreement with

Equation 7.

Equation 13

The result is an output voltage drop also at no load.

In order to avoid this no load voltage drop condition, the current sensing filter equivalent

resistance, i.e. RA//RB1, should fall in the range of 1 k

Ω -10 kΩ.

Figure 33.

Thermal compensation network

8.8

Soft-start and soft-end

The DAC voltage slew-rate at startup can be decreased, in order to limit the inrush current,

in GFX and VR11 supply mode. A soft-start capacitor CSS placed between the SSTART pin

and SGND is charged and discharged with 50 µA (only at startup). The resulting soft-start

capacitor voltage variation is exploited by the internal DAC to ramp up to the VIDs

programmed value (in GFX mode) or to the VBOOT default voltage (in VR11 mode), with

12.5 mV steps.

Figure 36 shows the soft-start VDAC voltage slew-rate vs. CSS capacitance.

If the SSTART pin is connected to SVCC, the VDAC ramp-up (and VOUT output voltage too)

is performed with a minimum 5 mV/µs voltage slew-rate. This function is performed in CPU

IMVP6.5 mode only.

Figure 34 and Figure 35 show the different soft-start mechanism for GFX mode and CPU

mode, assuming the following typical values for timing:

●

TON = 350 µs

●

TSTART depends on the soft-start programmed slew-rate and voltage; for CPU mode,

the soft-start slew-rate is 6.25 mV/µs (typ.) and VBOOT = 1.1 V, so TSTART = 176 µs

typ

●

TBOOT = 70 µs

●

TPG = 4 ms.

LKG

⋅

Rb1

CSNS

VOUT

AM02430v1

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