PM6652 datasheet(49/53 Pages) STMICROELECTRONICS

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PM6652

Layout guidelines

Doc ID 16867 Rev 5

49/53

Layout guidelines

The PM6652 has two separate grounds: PGND, the power ground, and SGND, the

reference for IC internal circuitry. A 2-separate-grounds layout is based on the following

guidelines:

●

Design an analog/signal ground plane on one inner layer, connect this area to SGND

and exposed pad (trough some vias)

●

Design one power ground plane on one internal layer. Connect the SGND (signal

ground) plane and PGND plane in one point (e.g. under the exposed pad or near the

low-side MOSFET source). If the PGND plane and SGND plane are in different layers,

use at least 2 vias for the connection. It is recommended not to use a resistor to

connect the PGND plane and SGND plane.

Alternatively, a single ground PCB can be designed, taking into account the following

suggestions (refer to

Figure 1):

●

Design one power ground plane on one internal layer

●

Connect all the components referred to SGND (R15, C2, C6, C8, R10, C9) with a

dedicated trace, then connect this trace to SGND (pin 9) and to the IC thermal pad

●

Connect the IC thermal pad directly to the power ground, through some vias.

Other suggestions for a good layout follow:

●

GSNS, VSNS: Route the remote feedback sensing nets coupled (7 mils separation)

and 18 mils wide. Keep 25 mils separation from other signals (this is an Intel

suggestion)

●

CSNS, VOUT: Keep the current sensing signals directly from the current sensing

element terminals (inductor pads, for DCR sensing, or precision resistor pads). Place

the L-DCR filter, if required, near the inductor and route the current sensing nets

coupled and far from noisy nets. Place the NTC thermistor, if required, as close as

possible to the inductor. Use the GND/SGND plane for shielding

●

IMON, IMONFB: Keep far from switching traces (use, if necessary, the GND/SGND

plane for shielding) and place the output R-C filter close to the CPU

●

LGATE, HGATE, PHASE: Design trace width > 20 mils and as short as possible (avoid

using vias if possible). Keep the ratio 3 mils_width/100 mils_lenght even for traces

longer than 500 mils (e.g. trace length: 2000 mils. design a trace width of about

60 mils). Keep far from signal traces to avoid noise coupling on signal traces. Place the

gate resistor near the MOSFET gate

●

BOOT: Place the ceramic capacitor close to the BOOT pin and PHASE pin; the trace

must be > 20 mils and the spacing with another signal trace > 20 mils. Minimize the

length of the loop between the PHASE pin and BOOT pin. Use at least 3 vias if a layer

change is required

●

SVCC, PVCC: Place the capacitor close to the SVCC/PVCC pin. Design trace width >=

20 mils. SVCC is internally connected to PVCC through a few

Ω resistor (3 Ω, typ.) so

SVCC doesn't need to be externally connected to +5 V rail.

PM6652 Datasheet(PDF) 49 Page - STMicroelectronics

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