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LAN9500AI Datasheet(PDF) 104 Page - Microchip Technology |
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LAN9500AI Datasheet(HTML) 104 Page - Microchip Technology |
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104 / 213 page  LAN950x DS00001875A-page 104 2010 - 2015 Microchip Technology Inc. FIGURE 5-34: DETAILED GPIOS 0-6 WAKE DETECTION LOGIC (LAN9500A/LAN9500AI) Note: The IME bit is in the Hardware Configuration Register (HW_CFG). General Purpose IO Configuration Reg- ister (GPIO_CFG) and General Purpose IO Wake Enable and Polarity Register (GPIO_WAKE) must be set accordingly. Diagram does not represent actual hardware implementation. FIGURE 5-35: DETAILED GPIO7 WAKE DETECTION LOGIC (LAN9500A/LAN9500AI) GPIOn_INT clear GPIOn GPIOPOLn Latch GPIODIRn GPIODn GPIOENn GPIOWKn GPIOn_DET IME GPIO7_INT clear GPIO7 GPIOPOL7 Latch GPIODIR7 GPIOD7 GPIOEN7 GPIOWK7 IME 0 1 0 1 GPIO7_DET SUSPEND0 SUSPEND3 PHY_LINK_EN PHY_LINK_UP |
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