LM98722CCMTSLASHNOPB datasheet(32/150 Pages) TI1

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PIXEL

VCLP

LM98722

SNAS487B – SEPTEMBER 2009 – REVISED MARCH 2015

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7.4.6 DC Coupled Applications

In some applications, particularly with CIS sensors, the output voltage is within a voltage range that will allow DC

coupling of the signal. When using Sample/Hold mode, DC coupling eliminates any problems with signal droop

across the line caused by voltage changes across the coupling capacitor. When DC coupling, the Auto CLPIN

should be disabled.

There are two ways of setting the proper DC levels in this type of application. If the sensor has a Vref output pin,

this can be connected to the VCLP pin of the LM98722. The internal VCLP generation should be disabled to

allow this external reference to set the Black Level for the chip close to the black pixel level of the sensor.

Many CIS sensors will not have a Vref output. In these applications, the internal VCLP voltage of the LM98722

can be set to the level that is closest to the black pixel level of the sensor.

Figure 9. Equivalent Input Switched Capacitance S/H Mode

In Sample and Hold Mode, the impedance of the analog input pins is dominated by the switched capacitance of

the CDS/Sample and Hold amplifier. The amplifier switched capacitance, shown as CS in Figure 8, and internal

parasitic capacitances can be estimated by a single capacitor switched between the analog input and the VCLP

reference pin for Sample and Hold mode. During each pixel cycle, the modeled capacitor, CSH, is charged to the

OSX-VCLP voltage then discharged. The average input current at the OSX pin can be calculated knowing the

input signal amplitude and the frequency of the pixel. If the application requires AC coupling of the CCD output to

the LM98722 analog inputs, the Sample and Hold Mode input bias current may degrade the DC bias point of the

coupling capacitor. To overcome this, Input Source Follower Buffers are available to isolate the larger Sample

and Hold Mode input bias currents from the analog input pin (as discussed in Input Source Follower Buffers). As

shown in CDS Mode section, the input bias current is much lower for CDS mode, eliminating the need for the

source follower buffers.

7.4.7 Input Source Follower Buffers

The OSR, OSG, OSB inputs each have an optional Source Follower Buffer which can be selected with Main

Configuration Register 3 at Page 0, Register 3, Bit[7]. These source followers provide a much higher impedance

seen at the inputs. In some configurations, such as Sample and Hold Mode with AC coupled inputs, the DC bias

point of the input nodes must remain as constant as possible over the entire length of the line to ensure a

uniform comparison to reference level (VCLP in this case). The Source Followers effectively isolate the AC input

coupling capacitor from the switched capacitor network internal to the LM98722’s Sample and Hold/ CDS

Amplifier. This results in a greatly reduced charge loss or gain on the AC Input coupling capacitor over the length

of a line, thereby preserving its DC bias point.

The Source Followers should only be used in the 1.2 V input range (i.e. Gain Mode Register at Page 1, Register

0, Bit[0] = 1, CDS Gain = 2x). Using the Source Followers in the 2.4 V (that is, Gain Mode Register at Page 1,

performance at the high and low ends of the input range).

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