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LM98722CCMT/NOPB Datasheet(PDF) 43 Page - Texas Instruments |
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LM98722CCMT/NOPB Datasheet(HTML) 43 Page - Texas Instruments |
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43 / 150 page  LM98722 www.ti.com SNAS487B – SEPTEMBER 2009 – REVISED MARCH 2015 In an ideal application, depicted in Figure 19, the Pixel output signal would be in phase with the timing signals that drove the CCD. The LM98722 input sampling clocks (CLAMP and SAMPLE) are adjustable within a pixel period. By default, the pixel period (or pixel “phase”) is defined to be in line with the input clock. As shown in the ideal case, Figure 19, CLAMP and SAMPLE can be properly adjusted to their ideal positions within the pixel phase, shown in Figure 19 at the stable region near the end of the pedestal and data phases. Figure 19. Clock Alignment in an Ideal Application However, in a real system, propagation delays exist in all stages of the signal chain. These propagation delays will lead to a shift in the CCD Pixel outputs with respect to the LM98722 input clock. The phase shift of the CCD Pixel output, demonstrated in Figure 20, can lead to significant sample timing issues if not properly corrected. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 43 Product Folder Links: LM98722 |
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