LM98722CCMTSLASHNOPB datasheet(64/150 Pages) TI1

64 / 150 page

LM98722

SNAS487B – SEPTEMBER 2009 – REVISED MARCH 2015

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7.4.15 CCD Timing Generator Master/Slave Modes

The internal Sensor Timing generator is capable of operating in Master Mode or in Slave Mode. The

Master/Slave operation is configured with the Master Mode Select bit (Page 0, Register 0x00, bit 1). In either

Master or Slave Mode, control bit data can be included in the LM98722 output data to indicate when each new

scan is starting as well as pixel information such as color, type (active, black, dummy, etc.), and the beginning of

each line.

7.4.15.1 Master Timing Generator Mode

In Master Timing Mode (Page 0, Register 0x00, bit 1 = 1), the LM98722 controls the entire CCD Timing

Generation based on INCLK and the Register Lock Bit (Page 0, Register 0, Bit 0) state. The Register Lock bit is

set by the user to initiate a new scan. The LM98722 controls when each new line of the scan begins and ends

based on the CCD Timing Generator register settings. Scanning is enabled as long as the Register Lock bit = 1.

The period of the line (integration time) is controlled by the SH Interval State Length settings (Page 3 Registers)

and the Line Length setting (Page 3, Registers 0x0D and 0x0E) as well as the Pixel Multiplier Factor (Page 2,

The line period from end of one SH Interval to the end of the next SH Interval is equal to:

Line Period = (Sum of SH Interval States x SH State Length Multiplier) + (Line Length Setting x Pixel Multiplier Factor)

pixels

(2)

7.4.15.2 Slave Timing Generator Mode

In Slave Timing Mode (Page 2, Register 0x00, bit 1 = 0), the LM98722 CCD Timing Generator is controlled by

the external SH_R pin. Each new line of a scan is initiated by an SH_R pulse. The period of the line (integration

time) is mainly controlled by the period of the incoming SH_R signal. The minimum period between SH_R pulses

should be at least the SH Interval duration as calculated in Equation 2, plus the number of pixels to be clocked

out of the CCD or CIS sensor.

Figure 40. SH_R to INCLK (PIXCLK or ADCCLK) Timing

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