LM98722CCMTSLASHNOPB datasheet(44/150 Pages) TI1

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LM98722

SNAS487B – SEPTEMBER 2009 – REVISED MARCH 2015

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Figure 20. CCD Output Phase Shift in a Real Application

In the default mode, the LM98722 sampling is performed during a clock period whose phase is aligned with the

input clock (ignoring any clock tree skew for the moment). The actual sampling clocks are adjustable within the

clock period, as shown in Figure 21 (shown for CDS mode in Figure 20) and further described in Internal Sample

Timing . As shown in Figure 20, the delay of the CCD Pixel output is shifted far enough that the fine CLAMP and

SAMPLE clocks cannot be placed in a stable portion of the waveform. To remedy this situation, the LM98722’s

Coarse Pixel Phase Alignment feature allows the designer to shift the entire phase of the analog front end with

respect to the input clock. This allows the designer to choose one of four sampling phases which best matches

the delay in the external circuitry. Once the “Coarse Pixel Phase” has been chosen, the designer can then fine

tune the sampling clocks using the fine adjustment (see Internal Sample Timing).

The four available Coarse Pixel Phases (PIXPHASE0 - PIXPHASE3) are depicted in Figure 21 (Mode 3),

Figure 22 (Mode 2) and Figure 23 (Mode 1). Also shown in the diagrams are the external input clock (INCLK)

and a typical CCD output delayed from the input clock.

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LM98722CCMT/NOPB Datasheet(PDF) 44 Page - Texas Instruments