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LM98722CCMT/NOPB Datasheet(PDF) 74 Page - Texas Instruments |
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LM98722CCMT/NOPB Datasheet(HTML) 74 Page - Texas Instruments |
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74 / 150 page ![]() LM98722 SNAS487B – SEPTEMBER 2009 – REVISED MARCH 2015 www.ti.com A summary and description of each of the modes and submodes is shown in Table 13. Table 13. Mode and Submode Summary MODE SUB_MODE Page 0, Register 0x05 Page 0, Register 0x05 DESCRIPTION Bits 4:3 Bits 2:1 00 Scrambler Disabled Full Scrambler Enabled. Sub-mode Settings Select: 00 send lvds_data[20:0] bitwise XOR with prs[20:0] 01 01 send prs[20:0] 10 send lvds_data[20:0] bitwise XOR with pprs[20:0] 11 send pprs[20:0] 1 bit scrambler with key of prs[0] send lvds_data[20:0] bitwise XOR with prs[0], with lvds_data[k] = 0 send prs[0] on lvds_out[k] k is selected with following settings: k = 0 (DB0 in CMOS and 714 modes, CB0 in flexible, 00 16 bit mode) 10 01 (TXOUT0 Disable = 0) k = 5 (DB0 (LSB) in flexible, 16 bit mode) 01 (TXOUT0 Disable = 1) k = 7 (DB2 (LSB) in flexible, 14 bit mode) 10 k = 16 (CB0 in 714 mode) 11 k = 20 (CB4 in 714 mode) 1 bit scrambler with key of lvds_data[k]. send lvds_data[20:0] bitwise XOR with lvds_data[k] with lvds_out[k] = lvds_data[k]: k = 0 (DB0 in CMOS and 714 modes, CB0 in flexible, 00 16 bit mode) 11 01 (TXOUT0 Disable = 0) k = 5 (DB0 (LSB) in flexible, 16 bit mode) 01 (TXOUT0 Disable = 1) k = 7 (DB2 (LSB) in flexible, 14 bit mode) 10 k = 16 (CB0 in 714 mode) 11 k = 20 (CB4 in 714 mode) 7.4.18.1 Mode 00: Scrambler Disabled Mode 00: Scrambler Disabled 7.4.18.2 Mode 01: Full Scrambler Using The Full 21-bit Pseudo Random Sequence There are 4 sub-modes: (a) the 21-bit output will be bit-wise XORed with the 21-bit serial pseudo-random sequence. i.e. lvds_data[20:0] ^ prs[20:0]; (b) the 21-bit serial pseudo random sequence will be output directly; (c) the 21-bit output will be bit-wise XORed with the 21-bit parallel pseudo-random sequence. i.e. lvds_data[20:0] ^ pprs[20:0]; (d) the 21-bit parallel pseudo random sequence will be output directly. In all sub-modes, the sequences start m clock cycles after the de-assertion of the bol where m is defined as the analog latencies in 1- ch, 2-ch and 3-ch modes. In other words, the output starts the same way as the up-count test pattern mode. Unlike the up-count test pattern mode, the 21-bit pseudo-random sequence runs at the ADC (same as TXCLK) rate, not pixel or line rate. 74 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: LM98722 |
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