CP3SP33SMSSLASHNOPB datasheet(180/407 Pages) TI1

Part #	CP3SP33SMS/NOPB

Description	Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces

PDF	407 Pages

Scroll/Zoom	100%

Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

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180 / 407 page

Bus

Signal

BIT

"NORMAL" BIT TIME

NEXT BIT

TSEG2

TSEG1

BIT

NEXT BIT

TSEG2

SJW

TSEG1

BIT TIME LENGTHENED BY SJW

CAN

Clock

DS029

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

The phase error is given by the deviation of the edge to the SYNC segment, measured in CAN clocks.

The value of the phase error is defined as:

e = 0, if the edge occurs within the SYNC segment

e > 0, if the edge occurs within TSEG1

e < 0, if the edge occurs within TSEG2 of previous bit

Re-synchronization is performed according to the following rules:

•

If the magnitude of e is less then or equal to the programmed value of SJW, resynchronization will

have the same effect as hard synchronization.

•

If e > SJW, TSEG1 will be lengthened by the value of the SJW (see Figure 22-12).

•

If e < –SJW, TSEG2 will be shortened by the value SJW (see Figure 22-13).

Figure 22-12. Resynchronization (e > SJW)

180

Dual CAN Interfaces

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CP3SP33SMS/NOPB Datasheet(PDF) 180 Page - Texas Instruments