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CP3SP33SMS/NOPB Datasheet(PDF) 204 Page - Texas Instruments

Part # CP3SP33SMS/NOPB
Description  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
PDF  407 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 204 Page - Texas Instruments

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CP3SP33
SNOSCW5 – MAY 2013
www.ti.com
15
5
4
3
2
0
GM[28:18]
RTR
IDE
GM[17:15]
0
R/W
The following are the bits for the GMSKXn register.
15
1M
0
GM[14:0]
XRTR
0
R/W
For all GMSKBn and GMSKXn register bits, the following applies:
0 – The incoming identifier bit must match the corresponding bit in the message buffer identifier
register.
1 – Accept 1 or 0 (“don’t care”) in the incoming ID bit independent from the corresponding bit in the
message buffer ID registers. The corresponding ID bit in the message buffer will be overwritten by
the incoming identifier bits.
When an extended frame is received from the CAN bus, all GMSKn bits GM28:0, IDE, RTR, and XRTR
are used to mask the incoming message. In this case, the RTR bit in the GMSKn register corresponds to
the SRR bit in the message. The XRTR bit in the GMSKn register corresponds to the RTR bit in the
message.
During the reception of standard frames only the GMSKn bits GM28:18, RTR, and IDE are used. In this
case, the GM28:18 bits in the GMSKn register correspond to the ID10:0 bits in the message.
Global Mask
GM28:18
RTR
IDE
GM17:0
XRTR
Standard Frame
ID10:0
RTR
IDE
Unused
Extended Frame
ID28:18
SRR
IDE
ID17:0
RTR
22.10.9 CAN Basic Mask Register n (BMSKBn/BMSKXn)
The BMSKBn and BMSKXn registers allow masking the buffer 14, or “don’t care” the incoming
extended/standard identifier bits, RTR/XRTR, and IDE. Throughout this document, the two 16-bit registers
BMSKBn and BMSKXn are referenced as a 32-bit register BMSKn.
The following are the bits for the BMSKXn register.
15
5
4
3
2
0
bM[28:18]
RTR
IDE
BM[17:15]
0
R/W
The following are the bits for the BMSKXn register.
15
1M
0
BM[14:0]
XRTR
0
R/W
For all BMSKBn and BMSKXn register bits the following applies:
0 – The incoming identifier bit must match the corresponding bit in the message buffer identifier
register.
1 – Accept 1 or 0 (“don’t care”) in the incoming ID bit independent from the corresponding bit in the
message buffer ID registers. The corresponding ID bit in the message buffer will be overwritten by
the incoming identifier bits.
204
Dual CAN Interfaces
Copyright © 2013, Texas Instruments Incorporated
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