CP3SP33SMSSLASHNOPB datasheet(200/407 Pages) TI1

200 / 407 page

Storage of Data Bytes

in the Buffer Memory

Sequence of Data Bytes on the Bus

CRC

Data8

Data7

Data6

Data5

Data4

Data3

Data2

Data1

Data2

Data1

Data4

Data3

Data6

Data5

Data8

Data7

Data Bytes

ADDR Offset

DS045

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

CANEN

The CAN Enable bit enables/disables the CAN module. When the CAN module is disabled,

all internal states and the TEC and REC counter registers are cleared. In addition the CAN

module clock is disabled. All CAN module control registers and the contents of the object

memory are left unchanged. Software must make sure that no message is pending for

transmission before the CAN module is disabled.

0 – CAN module is disabled.

1 – CAN module is enabled.

CTX

The Control Transmit bit configures the logic level of the CAN transmit pin CANnTX.

0 – Dominant state is 0; recessive state is 1.

1 – Dominant state is 1; recessive state is 0.

CRX

The Control Receive bit configures the logic level of the CAN receive pin CANnRX.

0 – Dominant state is 0; recessive state is 1.

1 – Dominant state is 1; recessive state is 0.

BUFFLOCK The Buffer Lock bit configures the buffer lock function. If this feature is enabled, a buffer

will be locked upon a successful frame reception. The buffer will be unlocked again by

writing RX_READY in the buffer status register, i.e., after reading data.

0 – Lock function is disabled for all buffers.

1 – Lock function is enabled for all buffers.

TSTPEN

The Time Stamp Enable bit enables or disables the time stamp synchronization function of

the CAN module.

0 – Time synchronization disabled. The Time Stamp counter value is not reset upon

reception or transmission of a message to/ from buffer 0.

1 – Time synchronization enabled. The Time Stamp counter value is reset upon reception

or transmission of a message to/from buffer 0.

DDIR

The Data Direction bit selects the direction the data bytes are transmitted and received.

The CAN module transmits and receives the CAN Data1 byte first and the Data8 byte last

(Data1, Data2,...,Data7, Data8). If the DDIR bit is clear, the data contents of a received

message is stored with the first byte at the highest data address and the last data at the

lowest data address (see Figure 69). The same applies for transmitted data.

0 – First byte at the highest address, subsequent bytes at lower addresses.

1 – First byte at the lowest address, subsequent bytes at higher addresses.

Figure 22-28. Data Direction Bit Clear

Setting the DDIR bit will cause the direction of the data storage to be reversed — the last byte received is

stored at the highest address and the first byte is stored at the lowest address, as shown in

Figure 22-29.

200

Dual CAN Interfaces

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