CP3SP33SMSSLASHNOPB datasheet(202/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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● IGNACK (Ignore Acknowledge).

● LOOPBACK (Loopback)

● INTERNAL (Internal Loopback).

● Write access to hidden receive buffer.

0 – Normal mode.

1 – Diagnostic features enabled.

EIT

The Error Interrupt Type bit controls the behavior of the Error Interrupt Pending bit

(CIPNDn.EIPND) when an error Interrupt is asserted, if enabled by the Error Interrupt

Enable bit (CIENn.EIEN).

0 – The EIPND bit is set on every error on the CAN bus.

1 – The EIPND bit is set only if the error state (CSTPNDn.NS) changes as a result of

incrementing either the receive or transmit error counter.

22.10.7 CAN Timing Register n (CTIMn)

The CTIMn register defines the configuration of the Bit Time Logic (BTL).

9 8

7 6

3 2

PSC

SJW

TSEG1

TSEG2

R/W

PSC

The Prescaler Configuration field specifies the CAN prescaler. The settings are shown in

Table 22-13.

Table 22-13. CAN Prescaler Settings

PSC6:0

Prescaler

000000

000001

000010

000011

000100

1111101

127

1111110

128

1111111

128

SJW

The Synchronization Jump Width field specifies the Synchronization Jump Width, which can be

programmed between 1 and 4 time quanta (see Table 22-14).

Table 22-14. SJW Setting

SJW(1)

Synchronization Jump Width (SJW)

1 time quantum

2 time quanta

3 time quanta

4 time quanta

(1)

The settings of SJW must be configured to be smaller or equal to

TSEG1 and TSEG2

202

Dual CAN Interfaces

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