CP3SP33SMSSLASHNOPB datasheet(215/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

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ADCRESLT Register—makes conversion results from the ADC available to the on-chip bus. The

ADCRESLT register includes the software-visible end of a 4-word FIFO used to queue conversion

results.

The configuration of the analog signal paths is controlled by fields in the ADCGCR register. The Input

Multiplexer is controlled by the MUX_CFG field. The Internal/External Multiplexer is controlled by the

ADCIN bit. The analog multiplexers for selecting the voltage references used by the ADC are controlled by

the PREF_CFG and NREF_CFG fields.

The output of the Input Multiplexer is available externally as the MUXOUT0 and MUXOUT1 signals. In

single-ended mode, only MUXOUT0 is used. In differential mode, MUXOUT0 is the positive side and

MUXOUT1 is the negative side. The MUXOUT0 and MUXOUT1 outputs and the ADCIN external analog

input are provided so that external signal conditioning circuits (such as filters) may be applied to the

analog signals before conversion. The MUXOUT0, MUXOUT1, and ADCIN signals are alternate functions

of the ADC inputs, so the number of available ADC inputs is reduced when these signals are used.

23.1.2 Operation

The TRIGGER block may be configured to initiate a conversion from either of these sources:

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External ASYNC Input—an edge on the ASYNC input triggers a conversion. This input may be

configured to be sensitive to rising or falling edges, as controlled by the POL bit in the ADCCNTRL

•

ADCSTART Register—writing any value to the ADCSTART register triggers a conversion.

The TRIGGER block incorporates a glitch filter to suppress transient spikes on the ASYNC input. The

TRIGGER block will recognize ASYNC pulse widths of 10 ns or greater. Once a trigger event has been

recognized, no further triggering is recognized until the conversion is completed.

When the ASYNC input is selected as the trigger source, it may be configured for automatic or non-

automatic mode, as controlled by the AUTO bit in the ADCCNTRL register:

•

Automatic Mode—a conversion is triggered by any qualified edge on the ASYNC input (unless a

conversion is already in progress).

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Non-Automatic Mode—before a conversion may be triggered from the ASYNC input, software must

“prime” the TRIGGER block by writing the ADCSTART register. Once the TRIGGER block is primed, a

conversion is triggered by any qualified edge on the ASYNC input. After the conversion is completed,

no additional trigger events will be recognized until software once again primes the TRIGGER block by

writing the ADCSTART register.

Once a trigger event is recognized, the DELAY1 block waits for a programmable delay specified in the

ADC_DELAY1 field of the ADCSCDLY register. Then, it asserts the Start signal to the ADC SEQUENCER

block.

When the Start signal is received, the ADC SEQUENCER block initiates the conversion in the ADC. After

the conversion is complete, the result is loaded into the FIFO, and the Done signal is asserted.

The ADCRESLT register includes the software-visible end of a 4-word FIFO, which allows up to 4

conversion results to be queued for reading. Reading the ADCRESLT register unloads the FIFO. If the

FIFO overflows, a bit is set in the ADCRESLT register, and the last conversion result is lost.

The Done signal is visible to software as the ADC_DONE bit in the ADCRESLT register. The Done signal

is also an input to the interrupt controller (IRQ9). The interrupt will be asserted whenever the FIFO is not

empty (but will deassert for one PCLK Clock period after the ADCRESLT register is read). Total

conversion time is 10 microseconds.

The Done signal is also an input to the Multi-Input Wake-Up unit (WUI53). The MIWU input is asserted

whenever the FIFO is not empty (but will deassert for one clock period after the ADCRESLT register is

read). The wake-up output is provided so that the ADC module can bring the system out of a low-power

mode when a conversion operation is completed. It asserts earlier than the interrupt output.

Analog-to-Digital Converter

215

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