CP3SP33SMSSLASHNOPB datasheet(218/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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Channel

(DIFF = 1)

MUX_CFG

(DIFF = 0)

1000

1001

1010 to 1111

Reserved

PREF_CFG

The Positive Voltage Reference Configuration field specifies the source of the ADC

positive voltage reference, as shown below:

PREF_CFG

PREF Source

Internal (ADVCC)

VREF

ADC0

ADC1

NREF_CFG

The Negative Voltage Reference Configuration field specifies the source of the ADC

negative voltage reference, as shown below:

NREF_CFG

NREF source

Internal (ADGND)

Reserved

ADC2

ADC3

MUXOUTEN

The MUXOUT Enable bit controls whether the output of the Input Multiplexer is available

externally. In single-ended mode, the MUXOUT0 pin is active and the MUXOUT1 pin is

disabled (TRI-STATE). In differential mode, both MUXOUT0 and MUXOUT1 are active.

0 – MUXOUT0 and MUXOUT1 disabled.

1 – MUXOUT0 and MUXOUT1 enabled.

INTEN

The Interrupt Enable bit controls whether the ADC interrupt (IRQ9) is enabled. When

enabled, the interrupt request is asserted when valid data is available in the ADCRESLT

0 – IRQ9 disabled.

1 – IRQ9 enabled.

23.4.2 ADC Auxiliary Configuration Register (ADCACR)

The ADCACR register is a 16-bit, read/write register used to control the clock configuration and report the

status of the ADC module. The APB bus master has read/write access to the ADCACR register. After

reset, this register is clear.

3 2

CNVT

TRG

PRM

Reserved

CLKDIV

CLKSEL

CLKSET

The Clock Select bit selects the clock source used by the DELAY2 block to generate the

ADC clock.

0 – ADC clock derived from PCLK Clock.

1 – ADC clock derived from Auxiliary Clock 1.

CLKDIV

The Clock Divisor field specifies the divisor applied to PCLK Clock to generate the 12 MHz

clock required by the ADC module. Only the PCLK Clock is affected by this divisor. The

divisor is not used when Auxiliary Clock 1 is selected as the clock source.

218

Analog-to-Digital Converter

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