Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

Preview PDF HTML

CP3SP33SMS/NOPB Datasheet(PDF) 381 Page - Texas Instruments

Part # CP3SP33SMS/NOPB
Description  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
PDF  407 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 381 Page - Texas Instruments

Back Button CP3SP33SMS/NOPB Datasheet HTML 377Page - Texas Instruments CP3SP33SMS/NOPB Datasheet HTML 378Page - Texas Instruments CP3SP33SMS/NOPB Datasheet HTML 379Page - Texas Instruments CP3SP33SMS/NOPB Datasheet HTML 380Page - Texas Instruments CP3SP33SMS/NOPB Datasheet HTML 381Page - Texas Instruments CP3SP33SMS/NOPB Datasheet HTML 382Page - Texas Instruments CP3SP33SMS/NOPB Datasheet HTML 383Page - Texas Instruments CP3SP33SMS/NOPB Datasheet HTML 384Page - Texas Instruments CP3SP33SMS/NOPB Datasheet HTML 385Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 381 / 407 page
background image
0
tCP
tCH
SRD
SRCLK
tCL
SRFS
DS116
1
0
1
2
tFSVH
tFSVL
tRDH
tRDS
CP3SP33
www.ti.com
SNOSCW5 – MAY 2013
36.10 Advanced Audio Interface (AAI) Timing
Table 36-5. Advanced Audio Interface (AAI) Signals
DESCRIPTION(1)
REFERENCE
MIN
MAX
UNIT
AAI INPUT SIGNALS
Before Falling Edge (FE) on SRCLK,
tRDS
Receive Data Setup Time
20
ns
See Figure 36-9 and Figure 36-11
tRDH
Receive Data Hold Time
After FE on SRCLK, See Figure 36-9 and Figure 36-11
20
ns
tFSS
Frame Sync Setup Time
Before Rising Edge (RE) on SRCLK , See Figure 36-9
20
ns
tFSH
Frame Sync Hold Time
After RE on SRCLK, See Figure 36-9
20
ns
AAI OUTPUT SIGNALS
tCP
Receive/Transmit Clock Period
RE on SRCLK/SCK to RE on SRCLK/SCK , SeeFigure 36-9
976.6
ns
tCL
Receive/Transmit Low Time
FE on SRCLK/SCK to RE on SRCLK/SCK , See Figure 36-9
488.3
ns
tCH
Receive/Transmit High Tim
RE on SRCLK/SCK to FE on SRCLK/SCK, See Figure 36-9
488.3
ns
RE on SRCLK/SCK to RE on SRFS/SFS , See Figure 36-9 and
tFSVH
Frame Sync Valid High
20
ns
Figure 36-11
RE on SRCLK/SCK to FE on SRFS/SFS, See Figure 36-9 and
tFSVL
Frame Sync Valid Low
20
ns
Figure 36-11
tTDV
Transmit Data Valid
RE on SCK to STD Valid, See Figure 36-10 and Figure 36-12
20
ns
(1)
Specified by design.
Figure 36-9. Receive Timing, Short Frame Sync
Copyright © 2013, Texas Instruments Incorporated
Electrical Specifications
381
Submit Documentation Feedback
Product Folder Links :CP3SP33



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com