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CP3SP33SMS/NOPB Datasheet(PDF) 379 Page - Texas Instruments

Part # CP3SP33SMS/NOPB
Description  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
PDF  407 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 379 Page - Texas Instruments

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PCLK
TXD
RXD
1
tCOv1
t
t
ls
lh
tCOv1
1
1
2
2
2
1
1
1
2
2
2
DS479
DS534
VCC
V
TRIP
Failure to have stable VCC
within minimum t
D
.
CP3SP33
www.ti.com
SNOSCW5 – MAY 2013
Figure 36-5. Bad Power-On Reset
36.8 UART Timing
Table 36-3. UART Signals
DESCRIPTION(1)
REFERENCE
MIN
MAX
UNIT
UART INPUT SIGNALS
tIs
Input setup time RXD (asynchronous mode)
Before Rising Edge (RE) on PCLK Clock,
ns
See Figure 36-6
tIh
Input hold time aRXD (asynchronous mode)
After RE on PCLK Clock, See Figure 36-6
ns
tCKX
CKX period (synchronous mode)
See Figure 36-7
250
ns
tRXS
RXD setup time (synchronous mode)
Before Falling Edge (FE) on CKX, See Figure 36-7
40
ns
tRXH
RXD hold time (synchronous mode)
Before Falling Edge (FE) on CKX, See Figure 36-7
40
ns
UART OUTPUT SIGNALS
tCOv1
TXD output valid (all signals with propagation
After RE on PCLK Clock, See Figure 36-6
35
ns
delay from CLKRE)
tTXD
TXD output valid
After RE on CKX, See Figure 36-7
40
ns
(1)
Specified by design.
Figure 36-6. UART Asynchronous Mode Timing
Copyright © 2013, Texas Instruments Incorporated
Electrical Specifications
379
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Product Folder Links :CP3SP33



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