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CP3SP33SMS/NOPB Datasheet(PDF) 376 Page - Texas Instruments

Part # CP3SP33SMS/NOPB
Description  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
PDF  407 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 376 Page - Texas Instruments

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CP3SP33
SNOSCW5 – MAY 2013
www.ti.com
36.5 ADC Electrical Characteristics
Temperature: –40°C
≤ TA ≤ 85°C)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VPREF
ADC Positive Reference Input(1)
1.62
1.98
V
VNREF
ADC Negative Reference Input (1)
0
0.25
V
ADC Input Range (1)
VNREF
VPREF
V
Clock Frequency
12
MHz
tC
Conversion Time (10-bit result)(1)
14
µs
INL
Integral Non-Linearity
±2
LSB
DNL
Differential Non-Linearity
±0.7
LSB
CADCIN
Total Capacitance of ADC Input (1)
9
20
pF
CADCINS
Switched Capacitance of ADC Input (1)
8
10
pF
RADCIN
Resistance of ADC Input Path (1)
0.1
12
k
Ω
CADCIN
Total Capacitance of ADC Reference Input (1)
50
100
pF
CADCINS
Switched Capacitance of ADC Reference Input (1)
8
10
pF
RADCIN
Resistance of ADC Reference Input Path(1)
0.2
0.6
k
Ω
(1)
Specified by design.
36.6 Output Signal Levels
The following output signals are powered by the digital IO supply (IOVCC) or, in the case of the Bluetooth
signals and port pins PF[6:0], the RF supply (RFVCC).
summarizes the states of the output signals during the reset state (when VCC power exists in the reset
state) and during the Power Save mode.
This device has many dedicated input signals which are not internally pulled to a supply; these must be
driven or tied off to a voltage lower than 0.5V or higher than IOVCC – 0.5V, to assure that the current in
Power Save mode does not exceed 1 mA. An input voltage between 0.5V and (VCC – 0.5V) may result in
power consumption exceeding 1 mA.
Table 36-1. Output Pins During Reset and Power-Save Mode
RESET STATE
SIGNALS ON A PIN
POWER SAVE MODE
COMMENTS
(with VCC)
PE[15:0]
TRI-STATE
Previous state
I/O ports will maintain their values when entering power-
save mode. There is no logic function to support this, so if
PF[15:0]
TRI-STATE
Previous state
the CPU and GPIO peripheral have a clock, the device is
PG[15:0]
TRI-STATE
Previous state
capable of altering the state of its port pins.
PH[7:0]
TRI-STATE
Previous state
376
Electrical Specifications
Copyright © 2013, Texas Instruments Incorporated
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