CP3SP33SMSSLASHNOPB datasheet(377/407 Pages) TI1

377 / 407 page

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

36.7 Clock and Reset Timing

Table 36-2. Clock and Reset Signals

DESCRIPTION(1)

REFERENCE

MIN

MAX

UNIT

CLOCK INPUT SIGNALS

tX1p

CLKIN period

Rising Edge (RE) to next RE, See Figure 36-1

83.33

tX1h

CLKIN high time, external clock

At 2 V level (both edges), See Figure 36-1

(0.5 Tclk) – 5

tX1l

CLKIN low time, external clock

At 0.8 V level (both edges), See Figure 36-1

(0.5 Tclk) – 5

tX2p

X2 period (2)

RE on X2 to next RE on X2, See Figure 36-1

10,000

tX2h

X2 high time, external clock

At 2V level (both edges), See Figure 36-1

(0.5 Tclk) – 500

tX2l

X2 low time, external clock

At 0.8V level (both edges), See Figure 36-1

(0.5 Tclk) – 500

CLOCK OUTPUT SIGNALS

tCLKp

HCLK Clock period (3)

Rising Edge (RE) to next RE, See Figure 36-1

42,667

16.6

tCLKh

HCLK Clock high time

At 2 V level (both edges), See Figure 36-1

21,333

20.83

tCLKl

HCLK Clock low time

At 0.8 V level (both edges), See Figure 36-1

21,333

20.83

tCLKr

HCLK Clock rise time on RE of CLKIN

At 2 V level (both edges), See Figure 36-1

tCLKf

HCLK Clock fall time on FE of CLKIN

At 0.8 V level (both edges), See Figure 36-1

RESET AND NMI INPUT SIGNALS

tIW

NMI Pulse Width, See (1)

NMI Falling Edge (FE) to RE

tRST

RESET Pulse Width

RESET FE to RE, See Figure 36-3

100

VTRIP

POR Rising Trigger Voltage

See Figure 36-4

1.11

1.54

tTRIP

VCC Rise Time to VTRIP

See Figure 36-4

VCC Rise Time from VTRIP to VCC

See Figure 36-4

800

µs

(1)

Specified by design.

(2)

Only when operating with an external square wave on X2CKI; otherwise a 32 kHz crystal network must be used between X2CKI and

X2CKO. If Slow Clock is internally generated from Main Clock, it may not exceed this limit.

(3)

Tclk is the actual clock period of the CPU clock used in the system.

The value of Tclk is system dependent.

The maximum cycle time in Power Save mode is 42,667 ns (= 1/12 MHz × 2 × 256).

The maximum cycle time in Active mode is 1333 ns (= 1/12 MHz × 16).

The minimum cycle time in Active mode is 16.6 ns (= 1/60 MHz).

Electrical Specifications

377

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB Datasheet(PDF) 377 Page - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 377 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL