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CP3SP33SMS/NOPB Datasheet(PDF) 375 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 375 Page - Texas Instruments |
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375 / 407 page  CP3SP33 www.ti.com SNOSCW5 – MAY 2013 36.4 Telematics Codec Electrical Characteristics Temperature: –40°C ≤ TA ≤ 85°C) PARAMETER(1) CONDITIONS MIN TYP MAX UNIT DUAL AUDIO ADC Lower (HPF Mode 1), Fs = 8 kHz 300 VADCPB Passband Hz Upper, Fs = 8 kHz 3300 VADCRIP Ripple Same as above, relative to 1 kHz ±0.25 dB Above 4.5 kHz 60 dB VADCSBA Stopband Attenuation HPF Notch, 50/60 Hz, HPF = 1 and HPF = 2, worst 55 dB case 1 kHz, –3 dBFS relative to idle noise, 85 dB Fs = 8 kHz, differential, A-weighted VADCSNR Signal-to-Noise Ratio Same as above, but single-ended 75 dB 1 kHz, –60 dB input, AES-17, VADCDR Dynamic Range 87 dB Fs = 8 kHz, differential, A-weighted 0.13 VRMS VADCLEVEL Input Level –3 dBFS, MICGAIN = 0, differential 0.354 VP-P(diff) Per application schematic, VRIPPLE = 200 mVP-P, VADCPSRR Power Supply Rejection Ratio 40 dB FRIPPLE = 217 Hz, MICGAIN = 0 Total Harmonic Distortion, VADCTHD+N –3 dB, 1 kHz input, relative to 0 dBFS, differential 0.015% ADC + microphone + noise Common Mode Voltage, VADCCM 0.9 V ADC + microphone VADCOFFSET Offset, microphone preamp Input referenced to MICGAIN = 1111 2.6 mV VADCRMICDIFF Differential Input Resistance TCMICxP to TCMICxN pins 150 k Ω VADCRMICSE Single-Ended Input Resistance TCMICxP/TCMICxN pin to AC ground (TCVBUFx pin) 75 k Ω VADCROVRP VREF Output Resistance 10 Ω Per application schematic, VADCPSRRVRP VREF PSRR 40 dB VRIPPLE = 200 mVP-P, FRIPPLE = 217 Hz Minimum 0 dB VADCGCR Gain Control Range Maximum 30 dB VADCSS Gain Control Step Size 2 dB VADCDELAY ADC Group Delay Mean from 300 Hz to 3.3 kHz 0.2 ms STEREO DAC SDACPB Passband Frequency -3 dB point, FIR optimized(2) 22 kHz SDACRIP Ripple DC to 20 kHz, Fs = 48 kHz, FIR optimized(2) ±0.08 dB SDACSBA Stop Band Attentuation Above Nyquist frequency, FIR optimized(2) 70 dB 1 kHz, 0 dBFS relative to idle noise, differential, SDACSNR Signal to Noise Ratio A-weighted, DAC asynchronous to HCLK Clock, 86 dB clocked from PLL 1 kHz, –60 dBFS, AES-17, differential, A-weighted, SDACDR Dynamic Range DAC synchronous to HCLK Clock, clocked from 12 95 dB MHz Main Clock SDACTHD+N Total Harmonic Distortion + noise –3 dB, 1 kHz input, relative to 0 dBFS, differential 0.01% SDACLEVEL Line Output Level 1 kHz, 20 k Ω load 1 VRMS SDACLOAD Minimum Line Output Load 1 kHz, 1 V RMS 20 k Ω SDACDLY DAC Group Delay Fs = 48 kHz 0.8 ms (1) Specified by design (2) DAC frequency response is tested using FIR compensation filter coefficients optimized for the CP3-DB-SP33 development board at a 48 kHz sampling frequency. At a 125× oversampling rate, these are C0 = 0121h, C1 = FB44h, C2 = 6C79h. At a 128× oversampling rate, these are C0 = 00E2h, C1 = FA7Dh, C2 = 6999h. Copyright © 2013, Texas Instruments Incorporated Electrical Specifications 375 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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