M38B53M4-059FP datasheet(221/355 Pages) MITSUBISHI

221 / 355 page

38B5 Group User’s Manual

APPLICATION

2-133

2.6 PWM

Fig. 2.6.3 Structure of PWM register (low-order)

Fig. 2.6.4 Structure of PWM control register

Functions

At reset R W

Undefined

PWM register (low-order)

b7 b6 b5 b4 b3 b2 b1 b0

PWM register (low-order)

(PWML: address 1516)

• Low-order 6 bits of PWM0 output data is set.

• The values set in this register is transferred to

the PWM latch at each PWM cycle period

(4096

µs).

(At f(XIN) = 4 MHz)

• When this register is read out, the value of the

PWM latch (low-order 6 bits) is read out.

Nothing is arranged for this bit. This bit is a

write disabled bit. When this bit is read out, the

contents are “0”.

• This bit indicates whether the transfer to the

PWM latch is completed.

0: Transfer is completed

1: Transfer is not completed

• This bit is set to “1” at writing.

PWM control register

b7 b6 b5 b4 b3 b2 b1 b0

PWM control register

(PWMCON: address 2616)

At reset R W

Functions

P87/PWM output

selection bit

0: I/O port

1: PWM output

Nothing is arranged for these bits. These are

write disabled bits. When these bits are read out,

the contents are “0”.

Name

M38B53M4-059FP Datasheet(PDF) 221 Page - Mitsubishi Electric Semiconductor

M38B53M4-059FP Datasheet(HTML) 221 Page - Mitsubishi Electric Semiconductor

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