TMS320VC5407 datasheet(38/110 Pages) TI

38 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

Reserved

XIOEN

RIOEN

FSXM

FSRM

CLKXM

CLKRM

R/W

SCLKME

CLKS STAT

DX STAT

DR STAT

FSXP

FSRP

CLKXP

CLKRP

R/W

LEGEND: R = Read, W = Write

Figure 3−14. Pin Control Register (PCR)

The selection of sample rate input clock is made by the combination of the CLKSM (bit 13 in SRGR2) bit value

and the SCLKME bit value as shown in Table 3−7.

Table 3−7. Sample Rate Input Clock Selection

SCLKME

CLKSM

SAMPLE RATE CLOCK MODE

Reserved (CLKS pin unavailable)

CPU clock

BCLKR

BCLKX

When the SCLKME bit is cleared to 0, the CLKSM bit is used, as before, to select either the CPU clock or the

CLKS pin (not bonded out on the 5407/5404 device package) as the sample rate input clock. Setting the

SCLKME bit to 1 enables the CLKSM bit to select between the BCLKR pin or BCLKX pin for the sample rate

input clock.

When either the BCLKR or CLKX is configured this way, the output buffer for the selected pin is automatically

disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the input of the

sample rate generator. Both the transmitter and receiver circuits can be synchronized to the sample rate

generator output by setting the CLKXM and CLKRM bits of the pin configuration register (PCR) to 1. Note that

the sample rate generator output will only be driven on the BCLKX pin since the BCLKR output buffer is

automatically disabled.

The McBSP is fully static and operates at arbitrary low clock frequencies. For maximum operating frequency,

see Section 5.14.

3.9

Hardware Timers

The 5407/5404 device features two 16-bit timing circuits with 4-bit prescalers. The timer counters are

decremented by one every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt is

generated. The timer can be stopped, restarted, reset, or disabled by specific status bits.

Both timers can be use to generate interrupts to the CPU, however, the second timer (Timer1) has its interrupt

combined with external interrupt 3 (INT3) in the interrupt flag register. Therefore, to use the Timer1 interrupt,

the INT3 input should be disabled (tied high), and to use the INT3 input, the timer should be disabled (placed

in reset).

Since the Timer1 output is multiplexed externally with the HINT output, the HPI must be disabled (HPIENA

input pin = 0) if the Timer1 output is to be used. The Timer1 output also has a dedicated enable bit in the

General Purpose I/O Control Register (GPIOCR) located at data memory address 003Ch. If the external

Timer1 output is to be used, in addition to disabling the HPI, the TOUT1 bit in the GPIOCR must also be set

to 1.

TMS320VC5407 Datasheet(PDF) 38 Page - Texas Instruments

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