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TMS320VC5407 Datasheet(PDF) 92 Page - Texas Instruments |
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TMS320VC5407 Datasheet(HTML) 92 Page - Texas Instruments |
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92 / 110 page  Electrical Specifications 92 November 2001 − Revised April 2004 SPRS007D 5.14 Multichannel Buffered Serial Port (McBSP) Timing 5.14.1 McBSP Transmit and Receive Timings Table 5−21 and Table 5−22 assume testing over recommended operating conditions (see Figure 5−21 and Figure 5−22). Table 5−21. McBSP T ransmit and Receive Timing Requirements† MIN MAX UNIT tc(BCKRX) Cycle time, BCLKR/X BCLKR/X ext 4P‡ ns tw(BCKRX) Pulse duration, BCLKR/X high or BCLKR/X low BCLKR/X ext 2P−1‡ ns t Setup time external BFSR high before BCLKR low BCLKR int 8 ns tsu(BFRH-BCKRL) Setup time, external BFSR high before BCLKR low BCLKR ext 1 ns t Hold time external BFSR high after BCLKR low BCLKR int 1 ns th(BCKRL-BFRH) Hold time, external BFSR high after BCLKR low BCLKR ext 2 ns t Setup time BDR valid before BCLKR low BCLKR int 7 ns tsu(BDRV-BCKRL) Setup time, BDR valid before BCLKR low BCLKR ext 1 ns t Hold time BDR valid after BCLKR low BCLKR int 2 ns th(BCKRL-BDRV) Hold time, BDR valid after BCLKR low BCLKR ext 3 ns t Setup time external BFSX high before BCLKX low BCLKX int 10 ns tsu(BFXH-BCKXL) Setup time, external BFSX high before BCLKX low BCLKX ext 1 ns t Hold time external BFSX high after BCLKX low BCLKX int 0 ns th(BCKXL-BFXH) Hold time, external BFSX high after BCLKX low BCLKX ext 2 ns tr(BCKRX) Rise time, BCKR/X BCLKR/X ext 6 ns tf(BCKRX) Fall time, BCKR/X BCLKR/X ext 6 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ P = 0.5 * processor clock |
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