TMS320VC5407 datasheet(53/110 Pages) TI

53 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

3.13.2

FIFO Control Register (FCR)

The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables

and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.

•

Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits

are written to or they are not programmed. Changing this bit clears the FIFOs.

•

Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not

cleared. The 1 that is written to this bit position is self clearing.

•

Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not

cleared. The 1 that is written to this bit position is self clearing.

•

Bits 3, 4, and 5: These three bits are reserved for future use.

•

Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 3−16).

Table 3−16. Receiver FIFO Trigger Level

BIT 7

BIT 6

RECEIVER FIFO

TRIGGER LEVEL (BYTES)

3.13.3

FIFO Interrupt Mode Operation

When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt

occurs as follows:

1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its

programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.

2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the

interrupt, it is cleared when the FIFO drops below the trigger level.

3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04)

interrupt.

4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO.

It is cleared when the FIFO is empty.

When the receiver FIFO and receiver interrupts are enabled:

1. FIFO time-out interrupt occurs if the following conditions exist:

a. At least one character is in the FIFO.

b. The most recent serial character was received more than four continuous character times ago (if two

stop bits are programmed, the second one is included in this time delay).

c. The most recent microprocessor read of the FIFO has occurred more than four continuous character

times before. This causes a maximum character received command to interrupt an issued delay of

160 ms at a 300 baud rate with a 12-bit character.

2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional

to the baud rate).

TMS320VC5407 Datasheet(PDF) 53 Page - Texas Instruments

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