TMS320VC5407 datasheet(49/110 Pages) TI

49 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

Table 3−13. DMA/CPU Channel Interrupt Selection

INT0SEL VALUE

IMR/IFR[6]

IMR/IFR[7]

IMR/IFR[10]

IMR/IFR[11]

00b (reset)

BRINT2

BXINT2

BRINT1

BXINT1

01b

BRINT2

BXINT2

DMAC2

DMAC3

10b

DMAC0

DMAC1

DMAC2

DMAC3

11b

Reserved

3.13 Universal Asynchronous Receiver/Transmitter (UART)

The UART peripheral is based on the industry-standard TL16C550B asynchronous communications element,

which in turn is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up

(character or TL16C450 mode), the UART can be placed in an alternate FIFO (TL16C550) mode. This relieves

the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and

transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.

The UART performs serial-to-parallel conversions on data received from a peripheral device or modem and

parallel-to-serial conversion on data received from the CPU. The CPU can read the UART status at any time.

The UART includes control capability and a processor interrupt system that can be tailored to minimize software

management of the communications link.

The UART includes a programmable baud rate generator capable of dividing the CPU clock by divisors from

1 to 65535 and producing a 16× reference clock for the internal transmitter and receiver logic. See Section 5.16

for detailed timing specifications for the UART.

TMS320VC5407 Datasheet(PDF) 49 Page - Texas Instruments