TMS320VC5407 datasheet(42/110 Pages) TI

42 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

Figure 3−17 shows the bus sequence for all memory writes and I/O writes. The accesses shown in

Figure 3−17 always require 3 CLKOUT cycles to complete.

WRITE

CLKOUT

A[22:0]

D[15:0]

R/W

PS/DS/IS

Leading

Cycle

Write

Cycle

MSTRB or IOSTRB

Trailing

Cycle

Figure 3−17. Memory Write and I/O Write Bus Sequence

The enhanced interface also provides the ability for DMA transfers to extend to external memory. For more

information on DMA capability, see the DMA sections that follow.

The enhanced interface improves the low-power performance already present on the TMS320C5000 DSP

platform by switching off the internal clocks to the interface when it is not being used. This power-saving feature

is automatic, requires no software setup, and causes no latency in the operation of the interface.

Additional features integrated in the enhanced interface are the ability to automatically insert bank-switching

cycles when crossing 32K memory boundaries (see Section 3.6.2), the ability to program up to 14 wait states

through software (see Section 3.6.1), and the ability to divide down CLKOUT by a factor of 1, 2, 3, or 4. Dividing

down CLKOUT provides an alternative to wait states when interfacing to slower external memory or peripheral

devices. While inserting wait states extends the bus sequence during read or write accesses, it does not slow

down the bus signal sequences at the beginning and the end of the access. Dividing down CLKOUT provides

a method of slowing the entire bus sequence when necessary. The CLKOUT divide-down factor is controlled

through the DIVFCT field in the bank-switching control register (BSCR) (see Table 3−5).

3.12 DMA Controller

The 5407/5404 direct memory access (DMA) controller transfers data between points in the memory map

without intervention by the CPU. The DMA allows movements of data to and from internal program/data

memory, internal peripherals (such as the McBSPs, but not the UART), or external memory devices to occur

in the background of CPU operation. The DMA has six independent programmable channels, allowing six

different contexts for DMA operation.

TMS320C5000 is a trademark of Texas Instruments.

TMS320VC5407 Datasheet(PDF) 42 Page - Texas Instruments