TMS320VC5407 datasheet(84/110 Pages) TI

84 / 110 page

Electrical Specifications

November 2001 − Revised April 2004

SPRS007D

5.9

Ready Timing for Externally Generated Wait States

Table 5−14 and Table 5−15 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5−10, Figure 5−11, Figure 5−12, and Figure 5−13).

Table 5−14. Ready Timing Requirements for Externally Generated Wait States†

MIN

MAX

UNIT

tsu(RDY)

Setup time, READY before CLKOUT low

th(RDY)

Hold time, READY after CLKOUT low

tv(RDY)MSTRB

Valid time, READY after MSTRB low‡

4H − 4

th(RDY)MSTRB

Hold time, READY after MSTRB low‡

tv(RDY)IOSTRB

Valid time, READY after IOSTRB low‡

4H − 4

th(RDY)IOSTRB

Hold time, READY after IOSTRB low‡

† The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,

at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.

‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.

Table 5−15. Ready Switching Characteristics for Externally Generated Wait States†

PARAMETER

MIN

MAX

UNIT

td(MSCL)

Delay time, MSC low to CLKOUT low

− 1

td(MSCH)

Delay time, CLKOUT low to MSC high

− 1

† The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,

at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.

TMS320VC5407 Datasheet(PDF) 84 Page - Texas Instruments