TMS320VC5407 datasheet(48/110 Pages) TI

48 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

3.12.10 DMA Interrupts

The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is

determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The available

modes are shown in Table 3−11.

Table 3−11. DMA Interrupts

MODE

DINM

IMOD

INTERRUPT

ABU (non-decrement)

At full buffer only

ABU (non-decrement)

At half buffer and full buffer

Multi frame

At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)

Multi frame

At end of frame and end of block (DMCTRn = 0)

Either

No interrupt generated

Either

No interrupt generated

3.12.11 DMA Controller Synchronization Events

The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN

bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events

and the DSYN values are shown in Table 3−12.

Table 3−12. DMA Synchronization Events

DSYN VALUE

DMA SYNCHRONIZATION EVENT

0000b

No synchronization used

0001b

McBSP0 receive event

0010b

McBSP0 transmit event

0011b

McBSP2 receive event

0100b

McBSP2 transmit event

0101b

McBSP1 receive event

0110b

McBSP1 transmit event

0111b

UART†

1000b

Reserved

1001b

Reserved

1010b

Reserved

1011b

Reserved

1100b

Reserved

1101b

Timer 0 interrupt event

1110b

External interrupt 3

1111b

Timer 1 interrupt event

† Note that the UART DMA synchronization event is usable as a synchronization event only, and is not usable

for transferring data to or from the UART. The DMA cannot be used to transfer data to or from the UART.

The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the

number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources.

DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When

the 5407/5404 is reset, the interrupts from these three DMA channels are deselected. The INT0SEL bit field

in the DMPREC register can be used to select these interrupts, as shown in Table 3−13.

TMS320VC5407 Datasheet(PDF) 48 Page - Texas Instruments

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