AIS2120SX datasheet(22/58 Pages) STMICROELECTRONICS

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Customer accessible data arrays (registers)

AIS1120SX / AIS2120SX

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DocID028312 Rev 3

2.4

REG_STATUS

Table 6. REG_STATUS_0

REG_STATUS_0 (address: 0x03)

Name

Bit#

R/W

Reset

state

Description

STATUS [1:0]

[7:6]

Status Error bits:

if = "00" device is in initialization phase (power-up,

configuration, fast offset cancellation);

if = "01" device is in normal mode (EOI = 1);

if = "10" device is test phase (0 g test or active self

test); EOI = 0;

if = "11" device is in initialization phase or normal

mode and some errors are detected: acceleration

data are disregarded due to errors in device.

TESTMODE_ENABLED

“0”: normal mode;

“1”: test mode

REG_CTRL_0_WR_ERR(1)

Will be set to '1' if write EOI = '1' attempt is made

with the device in +ve or -ve self-test (either CHX

or CHY).

Not used

“0” always

LOSS_CAP

Loss of capacitor:

if = "0" then loss of capacitor is not detected

(correct behavior);

if = "1" then loss of capacitor is detected (wrong

behavior).

Note:

1.LOSS_CAP check is done during the power-up

stage (~400 μs after POR) only.

2.Recommended VDD ramp rate >1 V/ms

3.It is recommended that LOSS_CAP flag (and all

other hardware flags) be reconfirmed with soft

POR after power up (END_OF_PWRUP='1').

END_OF_PWRUP

="1": end of power-up sequence; ready for self-

test.

RST_ACTIVE

Reset Active bit:

if = "0" then device is out of reset;

if = "1" then device has undergone a soft reset

sequence. Cleared by a read.

1. Bit not latched (cleared by any read command).

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