CC3220MODASM2MONR datasheet(51/100 Pages) TI1

51 / 100 page

T10

T11

TDI Input Valid

TDO Output Valid

TMS Input Valid

TDI Input Valid

TCK

TMS

TDI

TDO

TMS Input Valid

CC3220MOD, CC3220MODA

www.ti.com

SWRS206B – MARCH 2017 – REVISED AUGUST 2017

Submit Documentation Feedback

Product Folder Links: CC3220MOD CC3220MODA

Specifications

5.14.5.5 IEEE 1149.1 JTAG

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and

boundary scan architecture for digital integrated circuits and provides a standardized serial interface to

control the associated test logic. For detailed information on the operation of the JTAG port and TAP

controller, see the IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture.

Figure 5-14 shows the JTAG timing diagram.

Figure 5-14. JTAG Timing Diagram

Table 5-12 lists the JTAG timing parameters.

Table 5-12. JTAG Timing Parameters

ITEM

NAME

DESCRIPTION

MIN

MAX

UNIT

fTCK

Clock frequency

MHz

tTCK

Clock period

1 / fTCK

tCL

Clock low period

tTCK / 2

tCH

Clock high period

tTCK / 2

tTMS_SU

TMS setup time

tTMS_HO

TMS hold time

tTDI_SU

TDI setup time

T10

tTDI_HO

TDI hold time

T11

tTDO_HO

TDO hold time

CC3220MODASM2MONR Datasheet(PDF) 51 Page - Texas Instruments

CC3220MODASM2MONR Datasheet(HTML) 51 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL