CC3220MODASM2MONR datasheet(56/100 Pages) TI1

56 / 100 page

CC3220MOD, CC3220MODA

SWRS206B – MARCH 2017 – REVISED AUGUST 2017

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Product Folder Links: CC3220MOD CC3220MODA

Detailed Description

6.1

Overview

The CC3220MODx and CC3220MODAx are Wi-Fi Internet-on-a chip modules that consists of a Cortex-

M4 processor with a rich set of peripherals for diverse application requirements, a Wi-Fi network

processor, and power-management subsystems.

6.2

ARM

® Cortex®-M4 Processor Core Subsystem

The high-performance Cortex-M4 processor provides a low-cost platform that meets the needs of minimal

memory implementation, reduced pin count, and low power consumption, while delivering outstanding

computational performance and exceptional system response to interrupts.

•

The Cortex-M4 core has low-latency interrupt processing with the following features:

–

A 32-bit ARM® Thumb® instruction set optimized for embedded applications

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Handler and thread modes

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Low-latency interrupt handling by automatic processor state saving and restoration during entry and

exit

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Support for ARMv6 unaligned accesses

•

Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low-

latency interrupt processing. The NVIC includes the following features:

–

Bits of priority configurable from 3 to 8

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Dynamic reprioritization of interrupts

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Priority grouping that enables selection of preempting interrupt levels and nonpreempting interrupt

levels

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Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt

processing without the overhead of state saving and restoration between interrupts

–

Processor state automatically saved on interrupt entry and restored on interrupt exit with no

instruction overhead

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Wake-up interrupt controller (WIC) providing ultra-low-power sleep mode support

•

Bus interfaces:

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Advanced high-performance bus (AHB-Lite) interfaces: system bus interfaces

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Bit-band support for memory and select peripheral that includes atomic bit-band write and read

operations

•

Low-cost debug solution featuring:

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Debug access to all memory and registers in the system, including access to memory-mapped

devices, access to internal core registers when the core is halted, and access to debug control

registers even while SYSRESETn is asserted

–

Serial wire debug port (SW-DP) or serial wire JTAG debug port (SWJ-DP) debug access

–

Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches

CC3220MODASM2MONR Datasheet(PDF) 56 Page - Texas Instruments

CC3220MODASM2MONR Datasheet(HTML) 56 Page - Texas Instruments

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