MB90351ASPMC1 datasheet(63/83 Pages) CYPRESS

63 / 83 page

Document Number: 002-07872 Rev. *A

Page 63 of 83

MB90350 Series

15.4.6 Bus Timing (Write)

(TA = –40C to +105C, VCC = 5.0 V  10 %, VSS = 0.0 V, fCP ≤ 24 MHz)

* : n: Number of ready cycles

Parameter

Symbol

Condition

Value

Unit

Remarks

Min

Max

Valid address → WR

 time

tAVWL

A21 to A16, AD15

to AD00, WR

—

tCP15

—

WR pulse width

tWLWH WR

(n*+3/2)tCP  20

—

Valid data output → WR

 time

tDVWH

AD15 to AD00,

(n*+3/2)tCP  20

—

 → Data hold time

tWHDX

AD15 to AD00,

—

 → Address valid time

tWHAX

A21 to A16, WR

tCP/2  10

—

 → ALE  time

tWHLH

WR, ALE

tCP/2  15

—

 → CLK  time

tWLCH

WR, CLK

tCP/2  15

—

CLK

tWLCH

2.4 V

ALE

tWHLH

2.4 V

WR (WRL, WRH)

tWLWH

0.8 V

2.4 V

tAVWL

A21 to A16

0.8 V

2.4 V

0.8 V

tWHAX

AD15 to AD00

2.4 V

0.8 V

Address

0.8 V

2.4 V

Write data

tDVWH

0.8 V

2.4 V

tWHDX

For 1 cycle of auto-ready

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