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MB90351ASPMC1 Datasheet(PDF) 69 Page - Cypress Semiconductor |
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MB90351ASPMC1 Datasheet(HTML) 69 Page - Cypress Semiconductor |
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69 / 83 page ![]() Document Number: 002-07872 Rev. *A Page 69 of 83 MB90350 Series 15.4.13 I2C Timing (MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC AVCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V) (MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC AVCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V) (Device other than above: TA 40 °C to 125 °C, VCC AVCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V) *1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHDDAT has only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. *3 : A Fast-mode I2C -bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. *4 : For use at over 100 kHz, set the machine clock to at least 6 MHz. *5 : Refer to “Note of SDA, SCL set-up time”. Parameter Symbol Condition Standard-mode Fast-mode*4 Unit Min Max Min Max SCL clock frequency fSCL R 1.7 kΩ, C 50 pF*1 0 100 0 400 kHz Hold time for (repeated) START condition SDA↓→SCL↓ tHDSTA 4.0 — 0.6 — μs “L” width of the SCL clock tLOW 4.7 — 1.3 — μs “H” width of the SCL clock tHIGH 4.0 — 0.6 — μs Set-up time for a repeated START condition SCL↑→SDA↓ tSUSTA 4.7 — 0.6 — μs Data hold time SCL↓→SDA↓↑ tHDDAT 0 3.45*2 00.9*3 μs Data set-up time SDA↓↑→SCL↑ tSUDAT 250*5 —100*5 —ns Set-up time for STOP condition SCL↑→SDA↑ tSUSTO 4.0 — 0.6 — μs Bus free time between STOP condition and START condition tBUS 4.7 — 1.3 — μs SDA SCL 6 tcp ■ Note of SDA, SCL set-up time Input data set-up time |
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