MB90351ASPMC1 datasheet(22/83 Pages) CYPRESS

22 / 83 page

Document Number: 002-07872 Rev. *A

Page 22 of 83

MB90350 Series

9. Handling Devices

Special care is required for the following when handling the device :

■ Preventing latch-up

■ Treatment of unused pins

■ Using external clock

■ Precautions for when not using a sub clock signal

■ Notes on during operation of PLL clock mode

■ Power supply pins (VCC/VSS)

■ Pull-up/down resistors

■ Crystal Oscillator Circuit

■ Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

■ Connection of Unused Pins of A/D Converter

■ Notes on Energization

■ Stabilization of power supply voltage

■ Initialization

■ Port0 to port3 output during Power-on (External-bus mode)

■ Notes on using CAN Function

■ Flash security Function

■ Correspondence with TA   105 °C or more

■ Low voltage/CPU operation detection reset circuit

■ Internal CR oscillation circuit

9.1 Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions :

■ A voltage higher than VCC or lower than VSS is applied to an input or output pin.

■ A voltage higher than the rated voltage is applied between VCC pin and VSS pin.

■ The AVCC power supply is applied before the VCC voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

In using the devices, take sufficient care to avoid exceeding maximum ratings.

For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage.

9.2 Handling unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they

must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kΩ.

Unused I/O pins should be set to the output state and can be left open, or the input state with the above described connection.

MB90351ASPMC1 Datasheet(PDF) 22 Page - Cypress Semiconductor