L9300 datasheet(23/182 Pages) STMICROELECTRONICS

23 / 182 page

Since VDD2 could be used to track either VDD3 or VDD4 voltages, VDD2 enable and configuration pin is sensed

and latched at power up only after VDD3 and VDD4 voltages are above their own undervoltage thresholds: this is

intended to avoid wrong configuration latch during the VDD3 and VDD4 rising phase. Echo of the latched VDD2

configuration is available in the SPI registers.

VDD2 output is short to battery protected to avoid reverse current into VDD2_SUP pin: in case the protection is

triggered a diagnostic bit is set in the dedicated SPI register.

An out of regulation comparator is implemented: this comparator senses when the internal current limitation

circuitry is activated to regulate properly the output voltage due to either a low drop condition or an overcurrent

condition. Once out of regulation condition is detected a flag is set in SPI registers and latched until read. The

diagnostic is not masked during power-up phase.

VDD2 has a thermal protection with thermal sensors shared with TRKn regulators. In case the temperature

shutdown threshold is reached, and the regulator detects an out of regulation fault, it will be turned off and its

dedicated diagnostic bit will be set. Once the sensed temperature is decreased below the shutdown threshold

plus a thermal hysteresis, the regulator is automatically turned on with soft start function. T_SD_TRK is the bit

that latches the thermal shutdown and it is cleared on SPI read.

A dedicated disable SPI bit VDD2_DIS (default condition = 0) is present and it can be used to switch off the VDD2

regulator and avoid thermal on/off oscillations in case the short on output pin cannot be removed.

Figure 11. VDD2 linear or tracking regulator

VDD2

Tracking

Control

loop

(linear or

tracking)

Driver

VDD2_SUP

Tracking

VDD2

VDD2_SEL

VDD2

VDD2_SUP

GADG1007170948PS

8.2.2

VDD2 electrical characteristics

5.5 V ≤ VBATP ≤ 19 V; 5.5 V ≤ VDD2_SUP ≤ 19 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise noticed. All voltages

refer to GND pin. If VDD2_SUP < 6 V the regulator may enter in Rds ON mode where tracking error and line/load

regulation accuracy depend on regulator dropout.

Table 8. VDD2 electrical characteristics

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

IVDD2

Output load current

Application note

200

VDD2

CVDD2

Output capacitor

Application note Component &

temperature drift included

-25%

2.2

+25%

µF

VDD2

CVDD2 ESR

Output capacitor

maximum ESR

Application note f ≤ 150 kHz

0.01

Ω

VDD2

L9300

VDD2

DS12258 - Rev 4

page 23/182

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