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L9300 Datasheet(PDF) 30 Page - STMicroelectronics |
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L9300 Datasheet(HTML) 30 Page - STMicroelectronics |
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30 / 182 page  Symbol Parameter Test condition Min Typ Max Unit Pin CDRAIN3 EMI Drain Output capacitor Application note, VDRAIN=VBATP, capacitor required on the drain of external N-ch FET to prevent selfmode oscillations and to improve EMI robustness 1 µF CDRAIN3 EMI Drain Output capacitor Application note, VDRAIN=VDD1, capacitor required on the drain of external N-ch FET to prevent selfmode oscillations and to improve EMI robustness 0.1 µF R4up Feedback resistor range Application note 5 15 kΩ VDD4_SEL VDD4_SEL Regulated feedback voltage 0.01 A ≤ IVDD3 ≤ 1 A 0.8 – 2% 0.8 0.8 + 2% V VDD4_SEL VDD4_SEL line Line regulation VDRAIN 6 V to 19 V, IVDD4 = 0.01 A, 1 A -5 +5 mV VDD4_SEL VDD4_SEL load Load regulation IVDD4 = 0.01 A to 1 A, VDRAIN 6 V to 19 V -5 +5 mV VDD4_SEL VDD4_SEL _tr1 Transient output voltage 1 VDRAIN = 13 V, VDD4 ≥ 3.3 V, ∆IVDD4 =300 mA; dI/dt = 0.5 A/µs, CVDD4 = 5 µF, Guaranteed by design -5 +5 % VDD4_SEL VDD4_SEL _tr1 Transient output voltage 1 (No Reset Asserted) VDRAIN = 13 V, VDD4 < 3.3 V, ∆IVDD4 =300 mA; dI/dt = 0.5 A/µs, CVDD4 = 5 µF, Guaranteed by design -8 +8 % VDD4_SEL VDD4_SEL _tr2 Transient output voltage 2 (No Reset Asserted) VDRAIN step 12 V to 18 V; 18 V to 12 V, dVDRAIN/dt = 3 V/µs, IVDD4 = 0.01 A, 1 A, CVDD4 = 5 µF, Guaranteed by design -7 +7 % VDD4_SEL VDD4_G out Gate output voltage VBATP = 5.5 V, Open loop condition, VDD4_SEL = 0.7 V 12 16 V VDD4_G VDD4_G pd Gate internal pull down 100 1000 kΩ VDD4_G VDD4_PSSR PSSR VDRAIN = 6.5 V, IVDD3 = 500 mA, Vnoise = 1 Vpp, fnoise = 465 kHz, CVDD4 = 5 µF Guaranteed by design 20 dB VDD4 VDD4_SEL ovs_a Overshoot at power on IVDD4 = 10 mA, CVDD4 = 5 µF +4% V VDD4_SEL VDD4_SEL ovs_b Overshoot at VBATP step VBATP step from 5.5 V to 13 V during 10 µs, IVDD4 = 500 mA, CVDD4 = 5 µF, Guaranteed by design +10% V VDD4_SEL VDD4_SEL soft Slope control VDRAIN=VBATP = 13 V IVDD4 = 10 mA, CVDD4 = 4.7 µF 1 5 V/ms VDD4_SEL Diagnostic VDD4_UV VDD4_SEL undervoltage VDD4_SEL typ * (9.1/10) VDD4_SEL typ * (9.6/10) V VDD4_SEL VDD4_UV_ft VDD4_SEL undervoltage filter time Guaranteed by scan 8 16 µs VDD4_SEL VDD4_OV VDD4_SEL overvoltage VDD4_SEL typ * (11/10) VDD4_SEL typ * (11.8/10) V VDD4_SEL VDD4_OV_ft VDD4_SEL overvoltage filter time Guaranteed by scan 16 32 µs VDD4_SEL 1. If VDRAIN is supplied by VDD1, the value of the optional filtering capacitor must be chosen taking into account VDD1 current limitation value vs in-rush current during regulator power-up and supply transients. L9300 VDD4 DS12258 - Rev 4 page 30/182 |
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