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L9300 Datasheet(PDF) 27 Page - STMicroelectronics |
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L9300 Datasheet(HTML) 27 Page - STMicroelectronics |
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27 / 182 page  Table 10. VDD3 electrical characteristics Symbol Parameter Test condition Min Typ Max Unit Pin Ciss External FET input capacitor Application note: FET selection max input capacitance to guarantee stability 900 pF Gm External FET transconductance Application note: FET selection 20 mho Vth External FET threshold Application note: FET selection threshold voltage 3 V VDD3_Vout Output voltage Application note 0.8 5 V VDD3 IVDD3 Output load current Application note 0.01 1 A VDD3 CVDD3 Output capacitor Application note 5 22 40 µF VDD3 CVDD3_OPT Optional output capacitor(1) Application note max drivable cap in parallel with CVDD3 220 µF VDD3 CVDD3 ESR Output capacitor ESR Application note f ≤ 150 kHz 0.01 0,1 Ω VDD3 CDRAIN3 EMI Drain Output capacitor Application note, VDRAIN=VBATP Capacitor required on the drain of external N-channel FET to prevent self-mode oscillations and to improve EMI robustness 1 µF CDRAIN3 EMI Drain Output capacitor Application note, VDRAIN=VDD1 Capacitor required on the drain of external N-channel FET to prevent self-mode oscillations and to improve EMI robustness 0.1 µF R3up Feedback resistor range 5 15 kΩ VDD3_SEL VDD3 Regulator VDD3_SEL Regulated feedback voltage 0.01 A ≤ IVDD3 ≤ 1 A 0.8–2% 0.8 0.8+2% V VDD3_SEL VDD3_SEL line Line regulation VDRAIN 6 V to 19 V, IVDD3 = 0.01 A, 1 A -5 +5 mV VDD3_SEL VDD3_SEL load Load regulation IVDD3 = 0.01 A to 1 A, VDRAIN 6 V to 19 V -5 +5 mV VDD3_SEL VDD3_SEL _tr1 Transient output voltage 1 VDRAIN = 13 V, VDD3 ≥ 3.3 V, ∆IVDD3 =300 mA; dI/dt = 0.5 A/µs, CVDD3 = 5 µF, Guaranteed by design -5 +5 % VDD3_SEL VDD3_SEL _tr1 Transient output voltage 1 (No Reset Asserted) VDRAIN = 13 V, VDD3 < 3.3 V, ∆IVDD3 =300 mA; dI/dt = 0.5 A/µs, CVDD3 = 5 µF, Guaranteed by design -8 +8 % VDD3_SEL VDD3_SEL _tr2 Transient output voltage 2 (No Reset Asserted) VDRAIN step 12 V to 18 V; 18 V to 12 V, dVDRAIN/dt = 3 V/µs, IVDD3 = 0.01 A, 1 A, CVDD3 = 5 µF, Guaranteed by design -7 +7 % VDD3_SEL VDD3_G out Gate output voltage VBATP = 5.5 V, Open loop condition, VDD3_SEL = 0.7 V 12 16 V VDD3_G VDD3_G pd Gate internal pull down 100 1000 kΩ VDD3_G VDD3_PSSR PSSR VDRAIN = 6.5 V, IVDD3 = 500 mA, Vnoise = 1 Vpp, fnoise = 465 kHz, CVDD3 = 5 µF Guaranteed by design 20 dB VDD3 VDD3_SEL ovs_a Overshoot at power on IVDD3 = 10 mA, CVDD3 = 5 µF 4% V VDD3_SEL L9300 VDD3 DS12258 - Rev 4 page 27/182 |
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