NRF9160-SICA-R7 datasheet(121/400 Pages) NORDIC

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Peripherals

Similarly, when started and reception is enabled (in CONFIG.RXEN on page 134), the RXPTRUPD event

will be generated for every RXTXD.MAXCNT on page 137 received data words.

Left 0

Right 0

Left 1

RIght 1

Left 2

Right 2

Left 3

Right 3

Left 4

RXTXD.MAXCNT

Figure 24: Transmitting and receiving. CONFIG.FORMAT = Aligned,

CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo, RXTXD.MAXCNT = 1.

6.7.3 Left right clock (LRCK)

The Left Right Clock (LRCK), often referred to as "word clock", "sample clock" or "word select" in I2S

context, is the clock defining the frames in the serial bit streams sent and received on SDOUT and SDIN,

respectively.

In I2S mode, each frame contains one left and right sample pair, with the left sample being transferred

during the low half period of LRCK followed by the right sample being transferred during the high period of

LRCK.

In Aligned mode, each frame contains one left and right sample pair, with the left sample being

transferred during the high half period of LRCK followed by the right sample being transferred during the

low period of LRCK.

Consequently, the LRCK frequency is equivalent to the audio sample rate.

When operating in Master mode, the LRCK is generated from the MCK, and the frequency of LRCK is then

given as:

LRCK = MCK / CONFIG.RATIO

LRCK always toggles around the falling edge of the serial clock SCK.

6.7.4 Serial clock (SCK)

The serial clock (SCK), often referred to as the serial bit clock, pulses once for each data bit being

transferred on the serial data lines SDIN and SDOUT.

When operating in Master mode the SCK is generated from the MCK, and the frequency of SCK is then

given as:

SCK = 2 * LRCK * CONFIG.SWIDTH

The falling edge of the SCK falls on the toggling edge of LRCK.

When operating in Slave mode SCK is provided by the external I2S master.

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NRF9160-SICA-R7 Datasheet(PDF) 121 Page - Nordic Semiconductor