NRF9160-SICA-R7 datasheet(122/400 Pages) NORDIC

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Peripherals

6.7.5 Master clock (MCK)

The master clock (MCK) is the clock from which LRCK and SCK are derived when operating in Master mode.

The MCK is generated by an internal MCK generator. This generator always needs to be enabled when in

Master mode, but the generator can also be enabled when in Slave mode. Enabling the generator when

in slave mode can be useful in the case where the external Master is not able to generate its own master

clock.

The MCK generator is enabled/disabled in the register CONFIG.MCKEN on page 134, and the generator

is started or stopped by the START or STOP tasks.

In Master mode the LRCK and the SCK frequencies are closely related, as both are derived from MCK and

set indirectly through CONFIG.RATIO on page 135 and CONFIG.SWIDTH on page 136.

When configuring these registers, the user is responsible for fulfilling the following requirements:

1. SCK frequency can never exceed the MCK frequency, which can be formulated as:

CONFIG.RATIO >= 2 * CONFIG.SWIDTH

2. The MCK/LRCK ratio shall be a multiple of 2 * CONFIG.SWIDTH, which can be formulated as:

Integer = (CONFIG.RATIO / (2 * CONFIG.SWIDTH))

The MCK signal can be routed to an output pin (specified in PSEL.MCK) to supply external I2S devices that

require the MCK to be supplied from the outside.

When operating in Slave mode, the I2S module does not use the MCK and the MCK generator does not

need to be enabled.

MCK

LRCK

SCK

RATIO =

MCK

LRCK

SWIDTH

Figure 25: Relation between RATIO, MCK and LRCK.

Desired LRCK

[Hz]

CONFIG.SWIDTH

CONFIG.RATIO CONFIG.MCKFREQ

MCK [Hz]

LRCK [Hz]

LRCK error

[%]

16000

16Bit

32X

32MDIV63

507936.5

15873.0

-0.8

16000

16Bit

64X

32MDIV31

1032258.1

16129.0

0.8

16000

16Bit

256X

32MDIV8

4000000.0

15625.0

-2.3

32000

16Bit

32X

32MDIV31

1032258.1

32258.1

0.8

32000

16Bit

64X

32MDIV16

2000000.0

31250.0

-2.3

44100

16Bit

32X

32MDIV23

1391304.3

43478.3

-1.4

44100

16Bit

64X

32MDIV11

2909090.9

45454.5

3.1

Table 45: Configuration examples

6.7.6 Width, alignment and format

The CONFIG.SWIDTH register primarily defines the sample width of the data written to memory. In master

mode, it then also sets the amount of bits per frame. In Slave mode it controls padding/trimming if

required. Left, right, transmitted, and received samples always have the same width. The CONFIG.FORMAT

4418_1315 v2.0

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