NRF9160-SICA-R7 datasheet(124/400 Pages) NORDIC

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Peripherals

frame

left

LRCK

SCK

SDATA

left

right

Figure 27: Aligned format. CONFIG.SWIDTH equalling half-frame size.

6.7.7 EasyDMA

The I2S module implements EasyDMA for accessing internal Data RAM without CPU intervention.

The source and destination pointers for the TX and RX data are configured in TXD.PTR on page 137 and

RXD.PTR on page 137. The memory pointed to by these pointers will only be read or written when TX or

RX are enabled in CONFIG.TXEN on page 134 and CONFIG.RXEN on page 134.

The addresses written to the pointer registers TXD.PTR on page 137 and RXD.PTR on page 137 are

double-buffered in hardware, and these double buffers are updated for every RXTXD.MAXCNT on page

137 words (containing one or more samples) read/written from/to memory. The events TXPTRUPD and

RXPTRUPD are generated whenever the TXD.PTR and RXD.PTR are transferred to these double buffers.

If TXD.PTR on page 137 is not pointing to the Data RAM region when transmission is enabled, or

RXD.PTR on page 137 is not pointing to the Data RAM region when reception is enabled, an EasyDMA

transfer may result in a HardFault and/or memory corruption. See Memory on page 21 for more

information about the different memory regions.

Due to the nature of I2S, where the number of transmitted samples always equals the number of received

samples (at least when both TX and RX are enabled), one common register RXTXD.MAXCNT on page

137 is used for specifying the sizes of these two memory buffers. The size of the buffers is specified in

a number of 32-bit words. Such a 32-bit memory word can either contain four 8-bit samples, two 16-bit

samples or one right-aligned 24-bit sample sign extended to 32 bit.

In stereo mode (CONFIG.CHANNELS=Stereo), the samples are stored as "left and right sample pairs" in

memory. Figure Memory mapping for 8 bit stereo. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo.

on page 124, Memory mapping for 16 bit stereo. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Stereo.

on page 125 and Memory mapping for 24 bit stereo. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS =

Stereo. on page 125 show how the samples are mapped to memory in this mode. The mapping is valid

for both RX and TX.

In mono mode (CONFIG.CHANNELS=Left or Right), RX sample from only one channel in the frame is

stored in memory, the other channel sample is ignored. Illustrations Memory mapping for 8 bit mono.

CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left. on page 125, Memory mapping for 16 bit mono, left

channel only. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Left. on page 125 and Memory mapping

for 24 bit mono, left channel only. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Left. on page 126

show how RX samples are mapped to memory in this mode.

For TX, the same outgoing sample read from memory is transmitted on both left and right in a frame,

resulting in a mono output stream.

Right sample 1

x.PTR

x.PTR + 4

x.PTR + (n*2) - 4

Left sample 1

Right sample 0

Left sample 0

Right sample 3

Left sample 3

Right sample 2

Left sample 2

Right sample

n-1

Left sample

n-1

Right sample

n-2

Left sample

n-2

24 23

8 7

Figure 28: Memory mapping for 8 bit stereo. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo.

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